2) Now, assume for the delayed branch code from above exercise that our hardware can execute Static Dual Issue for any two instructions at once. Using reordering (with nops for padding), but no loop unrolling, schedule the instructions to make the loop take as few clock cycles as possible.
3) How many PCs would we need to implement hardware of Static Dual issue or any changes required in IF?
4) Would any changes be required in ID to support execution of two instructions at once?
5) Would any changes be required in EX to support execution of two instructions at once?
6) Would any changes be required in MEM to support execution of two instructions at once?
7) Would any changes be required in WB to support execution of two instructions at once?
8) Are there any new hazards in terms of type or their counts in this new processor? Please enumerate them and also how to resolve them (ie stalling or better options)
