COA-Lab 3 Complete Single Cycle CPU Solved

Based on (simple single-cycle CPU), add a memory unit to implement a complete single-cycle CPU which can run R-type, I-type and jump instructions. 

2. Requirement
(1)   Please use Icarus Verilog and GTKWave as your HDL simulator.

(2)   Please attach your names and student IDs as comment at the top of each file.

(3)   Top module’s name and IO port reference Lab2.

 

Reg_File[29] represents stack point. Initialize Reg_file[29] to 128 while others to

0.

You may add control signals to Decoder, e.g.

-  Branch_o

-  Jump_o

-  MemRead_o  

-  MemWrite_o  

-  MemtoReg_o

3. Requirement description
Lw instruction  memwrite is 0, memread is 1, regwrite is 1

Reg[rt] ← Mem[rs+imm]

 

Sw instruction memwrite is 1, memread is 0

Mem[rs+imm] ← Reg[rt]

 

Branch instruction branch is 1，and decide branch or not by do AND with the zero signal from ALU.

PC = PC + 4 + (sign_Imm <<2)

Jump instruction jump is 1

PC = {PC[31:28], address<<2}

 

NOP instruction
No operation – do nothing

 

4. Code  

(1) Basic Instruction:  

Lab2 instruction + mul, lw, sw, j, NOP

 

R-type
Op[31:26]
Rs[25:21]-
Rt[20:16]
Rd[15:11]
Shamt[10:6]
Func[5:0]
 

I-type
 
 
 
Op[31:26]
Rs[25:21]-
Rt[20:16]
Immediate[15:0]
 

Jump
 
 
 
Op[31:26]
 
 
Address[25:0]
 

instruction
op[31:26]
 
 
 
lw
6’b100011
Rs[25:21]
Rt[20:16]
Immediate[15:0]
sw
6’b101011
Rs[25:21]
Rt[20:16]
Immediate[15:0]
j
6’b000010
 
Address[25:0]
 

Mul is R-type instruction
0
Rs[25:21]-
Rt[20:16]
Rd[15:11]
0
6’b011000
 

NOP instruction
32 bits 0.

 

(2) Advance set 1:  

instruction
op
rs
rt
rd
shamt
func
jal
6’b000011
 
 
Address[25:0]
 
jr
6’b000000
rs
0
0
0
6’b001000
 

Jal: jump and link
In MIPS, the 31st register is used to save return address for function call.

Reg[31] saves PC+4 and address for jump

 

Reg[31] = PC + 4

PC = {PC[31:28], address[25:0]<<2}

 

Jr: jump to the address in the register rs
PC = Reg[rs];  

e.g.：In MIPS, return could be used by jr r31 to jump to return address from JAL

 

Example: when CPU executes function call,

       

0x00000000                  Fibonacci(4);

0x00000004                  Add r0, r0, r1

 

1

 

 3

0x00001000                  Fibonacci(){                                                                                         .                                     

2                            .    

0x00001020                  }

 

if you want to execute recursive function, you must use the stack point (Reg_File[29]).

First, store the register to memory and load back after function call has been finished. The second testbench CO_P3_test_data2.txt is the Fibonacci function. After it is done, r2 stores the final answer. Please refer to test2.txt.

 

(3) Advance set 2:

ble(branch less equal than): if( rs <= rt ) then branch

6’b000110
rs
rt
offset
 

bnez(branch non equal zero): if( rs != 0 ) then branch (It is same as bne)

6’b000101
rs
0
offset
 

bltz(branch less than zero): if( rs < 0 ) then branch

6’b000001
rs
0
offset
 

li(load immediate) by) addi.
You don't have to implement it, because it is similar to (and thus can be replaced
6’b001111
0
rt
immediate
 

 

5.     Testbench

CO_P3_test_data1.txt tests the basic instructions (50 pts.)  CO_P3_test_data2.txt tests the advanced set 1 (10 pts.).

Please refer to test1.txt and test2.txt for details. The following MIPS code is bubble sort. Please transform the MIPS code to machine code, store the machine code in CO_P3_test_data3.txt and run it (for testing advance set 2 (20 pts.)).

You don’t have to submit machine code.

 

    addu                  

    addi     addi     mul     j Jump bubble:

    li      li 

    mul outer:     addi     subu

    li  inner:     lw     lw

    ble

 
$t0, $0, $0

$t1, $0, 10

$t2, $0, 13

$t3, $t1, $t1

$t0, 10

$t1, 4

$t4, $t0, $t1

$t6, $0, 8

$t0, $t4, $t6 $t1, 0

$t2, 4($t0)

$t3, 0($t0)

$t2,$t3,no_swap
    sw     sw

    li no_swap:

    addi     subu     bltz

    j next_turn:

    bnez

    j

Jump:

    subu Loop:

    addu     beq

    j

End:
$t2, 0($t0)

$t3, 4($t0) $t1, 1

$t5, $0, 4

$t0, $t0, $t5 $t0, next_turn inner

$t1, outer

End

$t2, $t2,     $t1 

$t4, $t3,           $t2 $t1, $t2,             Loop bubble
 

             

6.     Reference architecture

This lab might be used extra signal to control. Please draw the architecture you designed on your report.