VLSI-Design-Course Project Solved

You are asked to design a 4-bit carry look ahead (CLA) adder as shown in Fig. 1(i). Different modules of the CLA-adder are shown in Fig. 1(ii). Each output sum bit needs to drive an inverter of size Wp/Wn = 20λ/10λ, where λ = 0.09µm. As shown in Fig. 1(iii), consider that input bits are available before the rising edge of the clock and the output should be computed and present at the next rising edge of the clock. You can choose any logic style (static, dynamic, mix) to implement the circuit.

 

Figure 1

CLA-Adder: If the numbers to be added are a4a3a2a1 and b4b3b2b1, then the propagate (pi) and generate (gi) signals for each bit position can be defined as (for i = 1, 2, 3, 4)

pi = ai ⊕ bi

gi = ai.bi

and the carry out (c(i+1)) of the ith bit position can be written as (assuming c0 = 0) follows:

c(i+1) = (pi.ci)+ gi, i = 1,2,3,4

Thus, c(i+1) can be expressed entirely in terms of the pi and gi functions and sum can be represented as follows:

sumi = pi ⊕ ci

1.        Briefly discuss your proposed structure for the adder.

2.        Give design details (topology and sizing) of each block (D-flip-flop, adder modules).

3.        Simulate each block and verify its functionality using NGSPICE.

4.        For D-flip-flop, find its setup time, hold time and clock to Q delay from NGSPICE simulations.

5.        Give stick diagrams of all unique gates in your design.

6.        Layout each block using MAGIC layout editor and previously given technology file. Perform post layout extraction and compare the results with schematic simulation.

7.        Integrate different block designed in previous steps and write the netlist for the full circuit shown in figure 1(i). Use NGSPICE and verify the functionality of the circuit. Attach the properly annotated waveforms. Report the worst case delay of your adder and maximum clock speed for which your design operates correctly.

8.        Give the floor plan of the layout for the complete circuit. Identify the horizontal and vertical pitches in the regular structures.

9.        Make layout of the complete circuit and extract the spice netlist. Repeat the simulations discussed above on the extracted netlist. Give a table comparing the schematic and postlayout simulation results.

10.    Report the delay of the CLA-adder and maximum clock frequency at which your circuit operates reliably.

11.    Using Verilog HDL write the structural description of your circuit and show the correctness of the functionality using simulations. Attach the required wave forms.

Suggested references:

1.    Digital Logic and Computer Design by Morris Mano.

2.    Computer Architecture and Organization by John P. Hayes.

3.    CMOS VLSI Design (fourth edition) by Weste and Harris.

4.    Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic.

 

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