VLSI-Design-Assignment-2 Solved

1.    Install MAGIC and do the inverter layout example shown in the tutorial. (No need to submit this part).

2.    Using NGSPICE, design a minimum sized CMOS inverter (L =0.18µm, Wn =0.27µm) such that the rise time and fall time (time taken to traverse from 10% to 90% of the transient ) are equal for a load capacitance of 100 fF.

(Hint: Adjust the width of the PMOS to get equal rise and fall times. Use .measure command fast and accurate measure. Use input pulse with 10 ps rise/fall and run transient with a resolution of few ps) (Practise problem; Not mandatory to submit)

3.    Consider a CMOS inverter with size 0W0, which has the following parameters : L = 0.18µm, Wn = W =1.8µm and Wp =2.5× W.

(a)     Using NGSPICE, plot VTC of inverter-1 (I1) for the case when the inverter is driving a same sized inverter (I2) as shown in Fig. 1.

 

Figure 1

(b)    As discussed in class, derive the expressions for noise-margins NMH and NML for a CMOS inverter.

(c)     From the VTC plot in (a) find the noise margin parameters (VIH,VIL,VOH,VOL) and calculate NMH and NML. Compare the noise-margins obtained from simulation with the theoretical values obtained in part (b) for which you can use VT values that you extracted in assignment-1.

(d)    Draw layout for case (a), extract the netlist and run post layout simulation to plot VTC of I1 and find its NMH and NML by clearly showing all noise-margin parameters on the plot. Tabulate theoretical, pre-layout and post-layout noise-margins for I1. Do you observe any difference (prelayout vs post-layout)? Comment.

4.    A typical CMOS inverter is considered to drive 4 similar inverters or having a fan-out of 4 (FO4 inverter). We want to characterize the delay of FO4 inverter, for which input and output waveforms should also

be typical in nature. Consider the figure 2, where an inverter with size 0W0 has following parameters : L =0.18µm, Wn = W =1.8µm and Wp =2.5× Wn. Write a net-list for the given configuration and apply a piece wise linear input at node ‘A’ as follows : Vin vin A 0 pwl (0 0V 0.5ns 1.8V 1.1ns 1.8V 1.5ns 0V 10ns 0V).

Vdd

 

Figure 2

(a)     As discussed in class, derive the expressions for rise-time (τrise) and fall-time (τfall) for an inverter in terms of noise margin parameters, supply voltage, threshold voltages of devices, Kn,Kp and load capacitance (CL). Calculate Kpτrise/CL and Knτfall/CL using the required values from the results obtained in problem 2(d), where K = µCoxWL .

(b)    Run transient simulation for 5 ns in step size of 10 ps for the given circuit and plot the signals at node ‘C’ and ‘D’ in the same graph. From the graphs, find the values of τrise and τfall at both the nodes C and D (You may consider 10% to 90% of the transient for finding rise/fall times. Use .measure for accuracy). Are they same? Comment.

(c)     Use .MEASURE command in NGSPICE and tabulate the propagation delays (input to output) of inverters I3 and I4. Are they same? Discuss.

(d)    Plot the supply current IDD as shown in the figure and explain the plot obtained.

(e)     Plot the ground current ISS as shown in the figure and explain the plot obtained.

5. Design a 31 stage ring oscillator (RO) using L =2λ, Wn =10λ and Wp =25λ, where λ =0.09µm.

(a)     Write NGSPICE netlist for the RO and find frequency (fRO) of oscillation and delay (τD) of a single inverter from simulation results. Do the values obtained from simulation results satisfy  , comment.

(b)    Draw an optimized layout for the 31 stage RO using MAGIC layout editor.

(Hint: Some useful magic commands- :getcell inverter-layout-name, :array <columns> <rows>, :upsidedown)

(c)     Extract the netlist of the RO from the layout with parasitics and use NGSPICE to find fRO and τD

(d)    Compare the pre-layout and post-layout simulation results and comment on the difference (if any).

 

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