All questions refer to the following figure.
1. Given RISC-V assembly instruction sequence: bne x22, x23, Else add x19, x20, x21 beq x0,x0,Exit
Else: lw x19, 0(x20)
Exit: …
Assuming the memory location of the first instruction (bne) is 0x1000F400, what are the values of the following control signals for each of the instructions?
2.Given following assembly instruction: and rd, rs1, rs2
(1) Which resources (blocks) perform a useful function for this instruction? (3 points)
(2) Which resources (blocks) produce no output for this instruction? Which resources produce output that is not used?
3. Consider the following instruction mix:
R-type
I-type (non-lw)
Load
Store
Branch
Jump
24%
28%
25%
10%
11%
2%
(1) What fraction of all instructions use data memory?
(2) What fraction of all instructions use instruction memory?
(3) What fraction of all instructions use the sign extend?
4. When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get “broken” and always read a logical 0. This is often called a “stuck-at-0” fault.
(1) Which instructions fail to operate correctly if the MemToReg wire is stuck at 0? (
(2) Which instructions fail to operate correctly if the ALUSrc wire is stuck at 0?
5.Problems in this exercise assume that the logic blocks used to implement a processor’s datapath have the following latencies:
I-Mem / D-Mem
Register File
Mux
ALU
Adder
Single gate
Register Read
Register Setup
Sign extend
Control
250 ps
150 ps
25 ps
200 ps
150 ps
5 ps
30 ps
20 ps
50 ps
50 ps
In above table, “Register Read” is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. “Register Setup” is the amount of time a register’s data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File.
(1) What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)? (5 points)
(2) What is the latency of lw?
(3) What is the latency of sw?
(4) What is the latency of beq?
(5) What is the latency of an arithmetic, logical, or shift I-type (non-load) instruction?
(6) What is the minimum clock period for this CPU?
6. Modify the single-cycle processor datapath to add a proposed new assembly instruction:
ss rs1, rs2, immediate #Store Sum
Operation: Mem[Reg[rs1]]=Reg[rs2]+immediate
