Ve311 Lab #3 -Solved

1  [Common-Source with Source Degeneration Amplifier]  

(a)  (RL = ∞) Design and build a common-source with source degeneration amplifier, which has a voltage gain Aυ > 5 , using 

NMOS (VN0104). Plot VOUT vs VIN. Is the voltage gain Aυ close to RD⁄RS? (Hint: First choose appropriate 𝑅𝐷 and 𝑅𝑆. Second, perform DC sweep to find out a 𝑉𝐼𝑁 at which the magnitude of slope is more than 5. At the same time, make sure the NMOS is in the saturation region. If not, change for another 𝑅𝐷 and 𝑅𝑆, and repeat the DC sweep again.)  

(b) ( RL = ∞ ) For Vin = VIN + 0.01sin(2π102 ∙ time) , plot Vout = VOUT + υout vs time. Confirm that the amplitude of υout is equal to 0.01 × Aυ. 

(c) (RL = 50 kΩ) For Vin = VIN + 0.01sin(2π102 ∙ time), plot Vout = VOUT + υout vs time. Does the amplitude of υout become smaller than 0.01 × Aυ? If so, explain the reasons. (Note: Make sure the NMOS remains in the saturation region.) 

2.     [Source Follower]  
(a)  (RL = ∞) Design and build a source follower, which has a voltage gain Aυ > 0.5, using NMOS (VN0104). Plot VOUT vs VIN. Is the voltage gain Aυ close to unity? (Hint: First choose appropriate 𝑅𝑆 . Second, perform DC sweep to find out a 𝑉𝐼𝑁 at which the magnitude of slope is more than 0.5. Here the NMOS is always in the saturation region.)  

(b) ( RL = ∞ ) For Vin = VIN + 0.05sin(2π102 ∙ time) , plot Vout = VOUT + υout vs time. Confirm that the amplitude of υout is equal to 0.05 × Aυ. 

(c) (RL = 50 kΩ) For Vin = VIN + 0.05sin(2π102 ∙ time), plot Vout = VOUT + υout vs time. Does the amplitude of υout still maintain around 0.05 × Aυ? If so, explain the reasons. 

Features
► Free from secondary breakdown

► Low power drive requirement

► Ease of paralleling

► Low CISS and fast switching speeds

► Excellent thermal stability

► Integral source-drain diode

► High input impedance and high gain

Applications
► Motor controls

► Converters

► Amplifiers

► Switches

► Power supply circuits

► Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)

Ordering Information

General Description
This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicongate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

Device
Package Option
 
Wafer / Die Options
 
TO-92
NW

(Die in wafer form)
NJ

(Die on adhesive tape)
ND

(Die in waffle pack)
VN0104
VN0104N3-G
VN1504NW
VN1504NJ
VN1504ND
For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’). Refer to Die Specification VF15 for layout and dimensions. 

Product Summary                                       Pin Configuration 

BVDSS/BVDGS

(V)
RDS(ON)

(max)

(Ω)
ID(ON)

(min)

(A)
40
3.0
2.0
Parameter
Value
Drain-to-source voltage
BVDSS
Drain-to-gate voltage
BVDGS
Gate-to-source voltage
±20V
Operating and storage temperature
-55OC to +150OC
SiVN 

1 0 4

YYWW
 Absolute Maximum Ratings
GATE

TO-92 (N3)

Product Marking
YY = Year Sealed 

 WW = Week Sealed 

Absolute Maximum Ratings are those values beyond which damage to the device              = “Green” Packaging 

may occur. Functional operation under these conditions is not implied. Continuous 

operation of the device at the absolute rating level may affect device reliability. All Package may or may not include the following marks: Si or  voltages are referenced to device ground.

TO-92 (N3)
 
Supertex inc.  ●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

Thermal Characteristics
Package
ID

(continuous)†

(mA)
ID

(pulsed)

(A)
Power Dissipation

@TC = 25OC

(W)
θjc

(OC/W)
θja

(OC/W)
IDR† (mA)
IDRM

(A)
TO-92
350
2.0
1.0
125
170
350
2.0
Notes:

†    ID (continuous) is limited by max rated Tj .

Electrical Characteristics (TA = 25OC unless otherwise specified)

Sym
Parameter
Min
Typ
Max
Units
Conditions
BVDSS
Drain-to-source breakdown voltage
40
-
-
V
VGS = 0V, ID = 1.0mA
VGS(th)
Gate threshold voltage
0.8
-
2.4
V
VGS = VDS, ID= 1.0mA
ΔVGS(th)
Change in VGS(th) with temperature
-
-3.8
-5.5
mV/OC
VGS = VDS, ID= 1.0mA
IGSS
Gate body leakage
-
-
100
nA
VGS = ± 20V, VDS = 0V
IDSS
Zero gate voltage drain current
-
-
1.0
µA
VGS = 0V, VDS = Max Rating
-
-
100
VDS = 0.8 Max Rating, 

VGS = 0V, TA = 125°C
ID(ON)
On-state drain current
0.5
1.0
-
A
VGS = 5.0V, VDS = 25V
2.0
2.5
-
VGS = 10V, VDS = 25V
RDS(ON)
Static drain-to-source on-state resistance
-
3.0
5.0
Ω
VGS = 5.0V, ID = 250mA
-
2.5
3.0
VGS = 10V, ID = 1.0A
ΔRDS(ON)
Change in RDS(ON) with temperature
-
0.70
1.0
%/OC
VGS = 10V, ID = 1.0A
GFS
Forward transductance
300
450
-
mmho
VDS = 25V, ID = 500mA
CISS
Input capacitance
-
55
65
pF
VGS = 0V,

VDS = 25V, f = 1.0MHz
COSS
Common source output capacitance
-
20
25
CRSS
Reverse transfer capacitance
-
5.0
8.0
td(ON)
Turn-on delay time 
-
3.0
5.0
ns
VDD = 25V,

ID = 1.0A,

RGEN = 25Ω
tr
Rise time
-
5.0
8.0
td(OFF)
Turn-off delay time
-
6.0
9.0
 
 
tf
Fall time
-
5.0
8.0
 
 
VSD
Diode forward voltage drop
-
1.2
1.8
V
VGS = 0V, ISD = 1.0A
trr
Reverse recovery time
-
400
-
ns
VGS = 0V, ISD = 1.0A
Notes:

1.     All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2.     All A.C. parameters sample tested.

Switching Waveforms and Test Circuit
 

Typical Performance Curves
Output Characteristics 

 

0                      10                     20                     30                     40

VDS (volts) 

Transconductance vs. Drain Current 
 

ID (amperes) 

 Maximum Rated Safe Operating Area 

VDS (volts) 

Saturation Characteristics 
 

0                 2.0               4.0                6.0               8.0                10 

VDS (volts) 

 
TC (OC) 

Thermal Response Characteristics 
 

0.001                 0.01                   0.1                    1.0                    10 

tP (seconds) 

Typical Performance Curves (cont.)
BVDSS Variation with Temperature
 

-50                     0                     50                   100                 150

Tj (OC)

Transfer Characteristics
 

Capacitance vs. Drain-to-Source Voltage


0

0                      10                    20                    30                   40

VDS (volts)

On-Resistance vs. Drain Current
 

ID (amperes)

V(th) and RDS Variation with Temperature
 

-50                    0                     50                   100                   150

Tj (OC)

Gate Drive Dynamic Characteristics
 

00                0.2              0.4              0.6              0.8              1.0 

QG (nanocoulombs)

3-Lead TO-92 Package Outline (N3)
 

                                                                                   Front View                                 Side View

Bottom View

Symbol
A
b
c
D
E
E1
e
e1
L
Dimensions (inches)
MIN
.170
.014†
.014†
.175
.125
.080
.095
.045
.500
NOM
-
-
MAX
.210
.022†
.022†
.205
.165
.105
.105
.055
.610*
JEDEC Registration TO-92.

* This dimension is not specified in the JEDEC drawing.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

Supertex Doc.#: DSPD-3TO92N3, Version E041009.

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) 
 ©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.                                                                                                                                  Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089 Doc.# DSFP-VN0104                                                                                         Tel: 408-222-8888 

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