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UWEE538-Homework 5 Difference Amplifier Analysis and Instrumentation Amplifier Analysis Solved
Problem 1: Difference amplifier analysis
Figure 1. Difference amplifier
A difference amplifier is driven by a sensor with source impedance Rs. Let Rf = 10k and Ri = 100. Assume ideal opamp behavior.
a) Derive an expression and determine a value for the DC differential input impedance Zin of the amplifier. Determine the source impedance Rs that results in a maximum of 0.1% attenuation of the input voltage.
b) Simulate the amplifier in Ltspice using the UniversalOpamp2 component (default parameters). Plot Zin up to 10MHz using AC analysis to show how it varies as a function of opamp gain.
Problem 2: Instrumentation amplifier analysis
Figure 2. Instrumentation amplifier
Assume the above opamps have a DC gain of 120dB and an fT of 1MHz. Nominal resistance values are Rfp
= Rfm = 4.95k, RG = 100, and R1 = R2 = 10k, all with 0.1% tolerance.
a) Determine the differential DC gain of the amplifier and the closed-loop bandwidth. Ignore resistor mismatch.
b) Based on the value of fT, what is the closed-loop gain error at 100Hz? Ignore mismatch.
c) Including the effect of resistor mismatch, what are the CMRR and the worst-case DC gain error? Assume infinite opamp open-loop gain.
d) Assume U1 and U2 have min/max input offset voltages of 100V but are otherwise identical. What is the maximum allowable offset of U3 to achieve a worst-case input-referred offset (the offset at Vout divided by the differential gain) of 250V? Ignore resistor mismatch.
e) Simulate the instrumentation amplifier in Ltspice using the UniversalOpamp2 component with appropriate Avol, GBW, and Vos values. Provide the following in your submission:
1. Image of your schematic showing the DC operating point (DC voltages at all nodes). Use the worst-case mismatch condition for the resistors. How much is the offset affected by resistor mismatch?
2. Plot showing the closed loop gain error at 100Hz using WC analysis. You can do this by selecting ‘list’ for the sweep type under AC analysis. Note that you need to run 128 iterations (27, where 7 is the number of resistors) to cover all mismatch combinations. Compare the contributions to gain error from finite opamp gain and resistor mismatch (i.e. which effect is more significant?).
3. Bode plots demonstrating closed-loop differential gain/phase and closed-loop commonmode gain/phase. For common-mode gain you should use the worst-case mismatch condition for the resistors.
Figure 1. Difference amplifier
A difference amplifier is driven by a sensor with source impedance Rs. Let Rf = 10k and Ri = 100. Assume ideal opamp behavior.
a) Derive an expression and determine a value for the DC differential input impedance Zin of the amplifier. Determine the source impedance Rs that results in a maximum of 0.1% attenuation of the input voltage.
b) Simulate the amplifier in Ltspice using the UniversalOpamp2 component (default parameters). Plot Zin up to 10MHz using AC analysis to show how it varies as a function of opamp gain.
Problem 2: Instrumentation amplifier analysis
Figure 2. Instrumentation amplifier
Assume the above opamps have a DC gain of 120dB and an fT of 1MHz. Nominal resistance values are Rfp
= Rfm = 4.95k, RG = 100, and R1 = R2 = 10k, all with 0.1% tolerance.
a) Determine the differential DC gain of the amplifier and the closed-loop bandwidth. Ignore resistor mismatch.
b) Based on the value of fT, what is the closed-loop gain error at 100Hz? Ignore mismatch.
c) Including the effect of resistor mismatch, what are the CMRR and the worst-case DC gain error? Assume infinite opamp open-loop gain.
d) Assume U1 and U2 have min/max input offset voltages of 100V but are otherwise identical. What is the maximum allowable offset of U3 to achieve a worst-case input-referred offset (the offset at Vout divided by the differential gain) of 250V? Ignore resistor mismatch.
e) Simulate the instrumentation amplifier in Ltspice using the UniversalOpamp2 component with appropriate Avol, GBW, and Vos values. Provide the following in your submission:
1. Image of your schematic showing the DC operating point (DC voltages at all nodes). Use the worst-case mismatch condition for the resistors. How much is the offset affected by resistor mismatch?
2. Plot showing the closed loop gain error at 100Hz using WC analysis. You can do this by selecting ‘list’ for the sweep type under AC analysis. Note that you need to run 128 iterations (27, where 7 is the number of resistors) to cover all mismatch combinations. Compare the contributions to gain error from finite opamp gain and resistor mismatch (i.e. which effect is more significant?).
3. Bode plots demonstrating closed-loop differential gain/phase and closed-loop commonmode gain/phase. For common-mode gain you should use the worst-case mismatch condition for the resistors.
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