Specifications
you are asked to design a gate-level combinational circuit that sorts five given numbers. The inputs of this circuit are five 6-bit unsigned digital values, denoted as i0, i1, i2, i3, i4. The outputs of the circuit, denoted as rank0(biggest), rank1, rank2, rank3, rank4(smallest), are all 6-bit unsigned numbers.
Below are some examples of the I/O:
Input
Output
i0
i1
i2
i3
i4
Rank0
Rank1
Rank2
Rank3
Rank4
0x09
0x1c
0x1d
0x26
0x2f
0x2f
0x26
0x1d
0x1c
0x09
0x07
0x0a
0x35
0x2c
0x37
0x37
0x35
0x2c
0x0a
0x07
0x1d
0x24
0x3a
0x36
0x26
0x3a
0x36
0x26
0x24
0x1d
[HINT] Bubble sort may not be fast enough, so try to use other sorting methods that are more hardware friendly.
There are some important things that you should notice:
Ø Your design should base on the standard cells in the lib.v. All logic operations in your design MUST consist of the standard cells instead of using the operands such as “+”, ”-”, “&”, “|”, “>”, and “<”. Note that the score of HW3 will be 0 if you use any of them.
Ø Design your homework in the given “sorting.v” file. You are NOT ALLOWED to change the filename and the header of the top module (i.e. the module name and the I/O ports).
Ø If your design contains more than one module, don’t create new file for them, just put those modules in “sorting.v.”
Ø The output waveform will be dumped to file “sorting.fsdb.” You can use nWave to examine it.
Ø For each set of input data, the test bench will allow your circuit to calculate the sorter outputs within 20ns. Once exceeding 20ns or detecting the correct answer from your circuit, the test bench will soon provide the new data set to your design until all 10000 data sets have been simulated.
Ø Circuit diagram
Plot the circuit diagram of your design. You are encouraged to plot it hierarchically so that the reader can understand your design easily.
Ø Discussion
Discuss about your design. For example, how do you sort these numbers, how do you improve your critical path.
