Problem Specification
Design a circuit with reset that computes the square root of an integer. There is one input, i.e., i_radicand with 10 bits, and there is one output o_root with 5 bits. Note that both radicand and root are unsigned integers(小數點後無條件捨去). The relation between inputs and outputs is
𝑟𝑜𝑜𝑡 = 𝑓𝑙𝑜𝑜𝑟 .
Note that the two output signals: “o_root [4:0]” and “o_finish” must be registered, i.e., they are outputs of DFFs (use module FD2 (positive edge) in lib.v ).
A possible architecture is as follows (not the best design):
Timing Diagram
Since a design can either be recursive or pipelined, the testbench provides two input strategies, i.e., recursive and pipeline.
1. Recursive
In the recursive input strategy, the circuit would be reset before every new radicand is input. Note that the radicand would be input at the next cycle right after reset.
2. Pipeline
In the pipeline input strategy, the circuit would only be reset once. After reset, a new radicand would be input every cycle. Also, o_finsh should maintain high once it was pulled up, and the order of input radicands and their corresponding roots should not be changed (First in, first out.).
Signals Description
Signal name
I/O
Width
Simple description
clk
Input
1
Clock signal.
rst_n
Input
1
Active low asynchronous reset.
i_radicand
Input
10
Radicand number.
o_root
Output
5
The square root of the radicand.
o_finsih
Output
1
Indicate that the calculation was finished.
number
Output
51
The number of transistors.
Design Rules
Those who do not design according to the following rules will not be graded.
➢ LUT-based designs are not allowed.
➢ There should be a reset signal for the register.
➢ You are free to add pipeline registers.
➢ You can loosen your simulation timing first, (i.e., `define CYCLE XXXX in the testbench.v), then shorten the clock period to find your critical path.
➢ Your design should be based on the standard cells in the lib.v. All logic operations in your design MUST consist of the standard cells instead of using the operands such as “+”, “-”, “&”, “|”, “>”, and “<”.
➢ Design your homework in the given “sqrt.v” file. You are NOT ALLOWED to change the filename and the header of the top module (i.e. the module name and the I/O ports).
➢ If your design contains more than one module, don’t create a new file for them, just put those modules in “sqrt
