1.
Two of the following cells are assigned to each of you. Everyone must do cells (10). Those whose student ID ends with 'k' must also do cell k. (Ex. If your ID is Bxx901123, you need to do (3) EO3, (10) FA1.)
(0) EN
(1) NR2
(2) OR2
(3) EO3
(4) AN3
(5) ND2
(6) AN2
(7) EO
(8) DRIVER
(9) IV
(10) FA1
For each cell,
a. Base on the layout view, draw transistor-level and gate-level circuit (NAND2
/ NOR2 / INV) diagrams (using PowerPoint, paint or 手畫)
b. Identify all inputs and outputs
c. List truth table
d. Revise the given netlist file to construct your cells. All PMOS transistors have
width 0.5um and length 0.1um. All NMOS transistors have width 0.25um and length 0.1um. Parameters of the 90nm model file (90nm_bulk.l) must be included during the simulation. The substrate of PMOS is connected to VDD and the substrate of NMOS is connected to VSS.
e. Run Hspice simulation on all possible input combinations. Assume
VDD=1.0V and VSS=0V. Use nWave to verify the truth table. Copy the I/O waveform to your report. State what you have observed.
f. Please discuss the problems you have encountered.
