This project will be relatively simple, but we would like you to get a clear idea of what you would like to build for your FSM. If you plan ahead now and make it scalable, it would keep things easier as the semester progresses.
In this project, you would build a Finite State Machine (FSM) using System Verilog.
Project Description/Requirements:
• Code your FSM in Behavioral System Verilog. Be creative in your FSM but at least 10 states are required.
• Choose your FSM for a practical application. Examples include Elevator operation, Vending Machines, Bank ATMs, Traffic controller, Convolutional Encoders, Surveillance drones, etc. Be creative; pick something interesting. By not specifying which FSM to use in this project, we are hoping to see many different implementations in the class. And we know that you are smart enough not to copy your code from web
• One test bench and at least one module for your FSM
• Clear comments to your code
