The MOS Transistor / Cadence
1
- For CAD simulation in Q2 assume VDD = 0.9 V, and use two fingers per transistor.
3. Figure shows a circuit used to measure the effective value of body effect factor (γ) (by measuring VT at different source voltages) and channel length modulation factor (λ) (by measuring Id at different Vds values). Assume in formula for threshold voltage (slide 7 lecture set 4 – MOS basics), 2φF = 0.88 V, and calculate VT0, γ, and λ for a device with 2 fingers. Can you justify the value of γ for the FinFET device you are simulating? Attach your CAD netlist, graphs and measurement data to your answers (25 points)
5. A CMOS inverter in 45 nm technology has a pull-up device that is 8λ:2λ and a pulldown device that is 4λ:2λ. It drives four identical inverters at its output. Compute the inverter delay (use Cg = 2 fF/um) and assume a ramp input. Re-calculate the delay if we have a chain of 4 inverters, i.e. 4 inverters in series (13 pts) Note: 2λ = 45nm
