1. Cell Library Layout (45 points) – Bonus
Introduction:
For this project, you will take your Verilog code from project 1 and 2, then synthesize it with 45nm standard cell library, and finally lay it out using Cadence Innovus tool.
Project Goals:
Auto-route and layout FSM using Innovus Test the final layout.
Project Requirements:
Assume a 10fF of load capacitance when simulating for all your outputs. Report Layout
1. Name, student number and project title on the first page of your project report.
2. Your report must include, but not limited to, the following:
a. Description regarding the function of your FSM design
b. Description in detail for all the inputs and outputs
c. Testing procedure
3. Complete layout with rulers (from Cadence) showing the dimensions of the full layout.
4. Output waveforms of the original Verilog code along with the waveforms from simulations of the FSM layout.
5. Test files to show that you tested your schematic properly.
2. Domino Logic (12 points)
1. (a) Determine the logic function OUT (3 points)
2. (b) Determine the reduction in voltage at the input of the inverter under the worst case charge sharing condition. Ceff = 1fF/um and Cg = 2 fF/um technology. (9 points)
(14 points) 4) (Power consumption) Analytically estimate the static (only for left circuit) and dynamic power consumption of the two inverters below (8 points) and compare your analytical results with that of simulation (8 points). Sketch VTC and show on the graph in which region we have power due to DC current, subthreshold current and short circuit current (4 points). Use 15 nm simulations and use an input frequency of 100 MHz for calculation/simulation. 10 fF is an explicit capacitor at the output of inverters.
(4 points)
6. (15 points) Interconnects
