In this lab you will design a Mealy FSM for the given sequence detector task and use Verilog to implement the sequence detector.
Prelab
Read the lab carefully and draw the state diagram of the FSM.
I. Mealy FSM
Design and implement the following FSM in Verilog :
A Mealy finite state machine has one input X and one output Z. The output Z = 1 occurs when the sequence 101 is observed on the input X, provided that the sequences 000 and 111 did not yet appear on X.
Once the sequence 000 is observed on X, the output Z becomes 0 and remains 0 indefinitely. Also, once the sequence 111 is observed on X, the output Z becomes 1 and remains 1 indefinitely.
