EEC180-Lab 2 Combinational Logic Design Using Verilog Solved

The purpose of this lab is to use Verilog to design combinational arithmetic circuits.  You will also learn how to write self-checking testbenches.

 

I.          Ripple-carry Adder 
 

A full adder (FA) has inputs a, b and ci (carry in) and produces outputs s (sum) and c0 (carry out).  c0 = a.b + a. ci + b.ci s= a Å  b  Å ci 

 

An n-bit ripple-carry adder can be designed by connecting full-adders in a chain with the carry in for a given stage being the carry out of the previous stage and the carry in of the least significant bit being a 0.

 

Perform the following steps:

1.      Write a behavioral model for a full adder in Verilog.   (Hint: an assign statement can describe each output equation.)

2.      Instantiate your full adder subcircuit in order to build an 8-bit ripple-carry adder. Add logic to produce an Overflow output, which should be set to 1 whenever the sum produced by the adder does not provide the correct signed (twos complement) value.

3.      Write a testbench to simulate your design for all possible input combinations. Note that for an 8-bit adder there are 216 (256 x 256) possible inputs.  See Appendix at the end of this document for an example of how to construct a testbench using a for loop in Verilog.

 

II.     Multiplication 
 

Figure 2 shows the traditional procedure for performing the multiplication P=A x B, where A and B are 4-bit unsigned binary numbers. Since each bit in B is either 1 or 0, the summands are either shifted versions of A or 0000. The Boolean AND operation can be used to multiply any two binary bits. Figure 3 shows an array multiplier circuit that implements P = A x B, where A and B are 4-bit unsigned binary numbers.  

  

 

Figure 2. Multiplication of Unsigned Binary Numbers

 

  

Figure 3. Array Multiplier Circuit Block Diagram

 

 

Perform the following steps:

 

1.      Write a structural model in Verilog that describes an 4x4 unsigned array multiplier that can be implemented on the Altera DE10-Lite board. Use switches SW7-4 to represent the number A and switches SW3-0 to represent the number B. Display the hex value of A on HEX3 and the hex value of B on HEX2. Display the result P = A x B on HEX1-0.  

 

2.      Compile your design in Quartus. Download your design to the Altera DE10-Lite board and test your circuit.

 

 

3.      Estimate the performance of your circuit in terms of the critical path using the timing analysis tool. The following is a step by step procedure to obtain the propagation delay between the input and output ports of your design:

 

Step 1. Timing netlist  
In this section, we will create a timing netlist, specify the delay model and operating conditions for the multiplier design.  

 

o   Go to Netlist section on top and click on Create Timing Netlist. The corresponding Timing Netlist window will pop-up.  

 

o   Select Fast-corner delay model and click OK.  

 

o   Next, go to Netlist - Set Operating Conditions, select MIN-Fast1200mV-0c operating condition and click OK.  

 

Step 2. Constraints  
In this section, we will set the maximum propagation delay constraints for the design.  

 

o   Go to Constraints - Set Maximum Delay and Set Maximum Delay window will pop-up.  

o   Click the name finder icon    and that will open up the Name Finder window.  

 

o   Select get_ports in collection and click List to list out all I/O ports.  

 

o   First, select all input ports, SW0, SW1..SW7 and transfer them to the second column using ‘’, which locks all the selected ports. Next, click ok to complete the From section in Set Maximum Delay window.  

 

o   Similarly, select all output ports HEX0[0:6] .. HEX3[0:6] and complete the To section in Set Maximum Delay window.

 

o   Next, set a Delay value of (say 30ns) and click Run. 

 

o   Finally, click on Update Timing Netlist in Tasks section to consider the timing constraint and re-generate timing reports.