Consider a design process for a duty-cycle corrector for a 1GHz input clock signal, denoted as clk_in. The output clock signal is denoted as clk_dcc. Once locked, clk_dcc will have a duty cycle very close to 50%.
(a) Draw a block diagram of your design and summarizing how you plan to achieve the duty-cycle correction with a paragraph.
(b) Realize the design as a synthesizable Verilog code. (Your design can be a mixed format containing both netlists and RTL codes). (Hint: you may need Tunable Delay Lines, A Phase Detector, and a Controller, etc.) In this homework, we only need to use simple TDL, e.g., path-selection-based TDL, and some cell-based Phase Detector from homework #1). Resolution is not a concern in this homework.
(c) Try to use Design Compiler to synthesize your design into standard-cell netlists.
(d) Verify the correctness of your design by running gate-level Verilog simulation using as accurate delay model as possible. (Note: you may need to use your behavior model from homework #1 for the PD part). Show the waveforms of clk_in and clk_dcc. Try the following input duty cycle samples for clk_in – {30%, 40%, 50%, 60%, 70%}.
(e) Try to use SOC Encounter to generate the layout of your design. What is the size of your layout?
(f) Try to re-do what you have done for problem (d), but back-annotated with the post-layout SDF information except the PD part. Compare your results with those derived in the pre-layout simulation.
