- Implement all the instructions in the RISC-V RV32I ISA that correspond to Load/Store (memory) operations.
You need to implement code for the `cpu` module, that will read in the instructions and execute them. For assignment 4 (Load/Store) you can assume that the program counter (PC) always increments by 4 on each clock cycle. For the assignment involving branching, this cannot be assumed and you will have to implement the proper changes in PC.
