- Assume the 32-b instruction is read in by a separate module called `dummydecoder` - this module creates a 6-b `opcode` that can be used by the ALU to decide what operation is needed. Since there are a total of < 30 ALU type instructions, 6 bits is ample here.
- The ALU itself should be a combinational module: it does not take a clock input, and only receives the two 32-b values to be operated upon, along with the opcode. It should generate a 32-b output value in a combinational manner.
- The Register File should be capable of generating two outputs in a combinational manner (output appears without waiting for a clock) and taking in one input and writing it into a register (this has to be clocked).
### Dummy Decoder
In practice, you will later design a decoder module that generates most of the control signals for the datapath. Now you can keep it simple and just generate the register select codes, and an `opcode`. This is left as a choice to you.
In principle, you could choose to use a different opcode encoding of more or less than 6 bits, but for this assignment the requirement is to use 6 bits so that it is compatible with the test bench.
**Important**: One more thing the decoder does is to select between the Immediate operand (which would be present in the instruction itself) and one of the register values (`rv2` because of the way the instructions are encoded). Again, in practice, you will have a MUX in the datapath that does this selection. One way to implement it is to send the output of the RegFile back into the decoder, where the selection between this value and the immediate value happens.
