PROBLEM 1.1:
Write the truth table for the following gates:
(a) AND (d) NAND
(b) OR (e) XOR (c) NOR (f) XNOR
PROBLEM 1.2:
Define De Morgan’s law and show how it would be used to simplify the following Boolean equation.
Y = A + AB + AB + A + B (1)
PROBLEM 1.3:
Given the following Truth Table that represents a 16QAM signal.
I
Q
Symbol
I
Q
Symbol
-3
-3
0000
1
-3
1100
-3
-1
0001
1
-1
1101
-3
1
0011
1
1
1111
-3
3
0010
1
3
1110
-1
-3
0100
3
-3
1000
-1
-1
0101
3
-1
1001
-1
1
0111
3
1
1011
-1
3
0110
3
3
1010
Find:
(a) The Boolean Equation for each bit of the Symbol using a Karnaugh Map.
(b) Create a schematic of digital gates to represent the Boolean Equation. Label each gate andeach wire.
(c) Implement the schematic in Verilog using Altera’s Schematic Entry tool
(d) Program the schematic in Verilog using a text based tool.
