ECE380-Lab 2 Solved

Part I. VHDL for a simple circuit 

 

The objective of this practice is to generate and simulate (test) different type of design for a simple combinational logic. Please use three individual projects for the following tasks.  

 

 

a 
b 
c 
f 
 
0 
0 
1 
0 
1 
0 
 
1 
0 
0 
1 
1 
1 
 
0 
0 
0 
0 
1 
1 
 
1 
0 
1 
1 
1 
0 
 

 

Design A: Write a VHDL model (entity and architecture) to describe the logic specify by the above truth table. Describe the circuit with AND, OR, NOT in your architecture body.  

-        Create a project using VHDL, following lab 01 related steps.

 

-        Test your design using functional simulations. You need to generate all the combinations for those three inputs, i.e., 000, 001, 010, …,111.  

 

  

 

 

 

-        With a ready VHDL code, compile (short-cut key, Ctrl+K).  

-        Generate waveform simulations. Follow the same procedure in lab 1 to open .vwf file. List all the input (A, B, C), and output (f) nodes and insert them in the waveform editor. Since there are 3 inputs, number of possible inputs are 23=8.  

 

-        Select the signal you want to edit in the waveform editor

  

 

-        Click the icon “overwrite clock” on the toolbar

  

 

-        Set the period of signal and click OK. A clock waveform will be generated in the waveform editor

  

 

-        Set the period of signals A, B and C to 20, 40, and 80 ns respectively. Set the end time to 160 ns.  

 

-        Run functional simulations to generate the output waveform and save the screenshot of .vwf showing all the inputs and output.

 

Note: Similar tutorial materials can be found in Introduction to Simulation of VHDL Designs, supplement_quartusii_simulation_vhdl.pdf, in lab 01.

 

 

Design B: Create a schematic based on the NOR gate implementation.  

-        Test/simulate this design.

-        Open .vwf and insert the clock signals for A, B, and C inputs as in Designs A and B.

-        Perform functional simulations.

-        Compare the generated output waveform with those from Designs A and B.  

 

 

Part II. Generate a flashing LED 

 

In this part, you are asked to follow a simple design and upload the design to the Altera’s DE1 board. This simple design drives a LED flashing at a rate of one second.   

 

The DE1 board provides 50 MHz clock signals. To generate the required one-second period clock, you need to use a multi-bit counter, which can be implemented by a library module LPM_COUNTER, in Quartus II, to divide the onboard 50 MHz clock. The customized LPM_COUNTER uses 26 bits can count from 0 to 50,000-1. The counter reduces the frequency of the 50 MHz clock signal and its output behaves as a clock signal changing at the rate of one second.  

 

Requirement: Demonstrate a LED flashing at 1 second rate.

 

Step 1: Create a new project named frequency. Under the project, create a new BDF file and save the file as frequency.bdf.  

 

Step 2: Configure lpm_conter and draw the schematics

        -    Go to Library à Arithmetics à lpm_Counter

When you click on lpm_counter, a dialogue window “Save IP variation” appears as below:  

 

  

 

Save it under the project ‘frequency’ as lpm_counter1(C:\altera\16.0\quartus\frequency\lpm-counter1). Make sure you save it as VHDL and click OK.  

 

After clicking OK, MegaWizard Plug-in manager appears where parameters of the counter can be changed. It goes through the following six steps:  

 

1.     Change the number of bits to 26, click Next.  

  

 

 

 

2.     Insert 50,000,000 as modulus with a count modulus, click Next.  

   

 

 

 

3.     Click Next.

    

 

 

4.     Click Next.

  

 

 

 

 

5.     Select the type of files you want Quartus II to generate. Select “VHDL component declaration file”, “symbol file” and then click Finish. 

 

  

 

 

6.     After that, click Yes to add lpm_counter1 file to the existing projects.

 

  

 

 

Once added, lpm_counter1 can be found in the symbol tool and can be dragged on the block editor.

 

 

 

Step3: With lpm_counter1 in the block editor, fetch an Input pin, connect it with lpm_conter1, and name the pin as Clock. Connect the wire on the output side and double click the wire to highlight it into blue. The highlighted blue indicates that the wire can be named. Name it as q[25..0]. Further, name the output pin as q[25].

 

  

 

 

Step 3: Save and compile the project.  

 

Step 4: Pin assignment. After the project is successfully compiled, assign the DE1 pins to both input and output of your design.  

 

 

Click on pin planner and the following image appears.  

 

  

View of DE 1 board before assigning pins
 

Click on location and type in PIN_AF14 to assign pin to clock signal (input) and type in PIN_V16 to assign q[25] (output).  

 

The details of PIN numbers of clock input signal (Page 20) and output (Page 24) can be found in DE1 board manual (distributed along this lab document).  

   

  

View of DE 1 board after assigning pins
 

 

Step 5: Compile again and upload the program to DE 1 board  

-        Switch ON the DE1 Board using the red button  

-        In Quartus II, go to Tools-à Programmerà Hardware Setup-àselect ‘DE-SoC’  

-        Make sure Mode is ‘JTAG’

-        Click auto-detect

-        Select 5CSEMA

  

 

-        Right click on 5CSEMA5-àadd file-àoutput files-àselect the frequency.sof file (in output files of the directory)

-        Click on the Program/Configure checkbox on the 5CSEMA5 line -           Click ‘Start’.  

-        At this point, your program has been transferred to the DE1 board. You should see the LED flashing on DE1 Board.  

 

  

 

 

             

HW #2  

 

1)Use two types of methods, algebraic manipulation and truth tables, to prove the following Boolean statements.  

 

a)    f (x1,x2) =∏M(0, 3) =∑m(1, 2) (Note these are two input functions)

 

 

b)    𝑥𝑥̅𝑦𝑦𝑦𝑦 + 𝑥𝑥𝑦𝑦𝑦𝑦 + 𝑥𝑥𝑦𝑦𝑦𝑦̅ + 𝑥𝑥𝑦𝑦𝑦𝑦 = 𝑥𝑥𝑦𝑦 + 𝑦𝑦𝑦𝑦 + 𝑥𝑥𝑦𝑦 

 

 

c)    f (x1,x2) =∑m(0,1,2) =M3(Assume that the minterms and maxterms are for the two input functions).  

 

 

 

 

2)  Draw two types of the AND-OR schematic for the following function: 𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑦𝑦) = ∏ 𝑀𝑀(0, 3, 6); a) Product-Of-Sums (POSs) form, or the maxterm form. b) Sum-Of-Products (SOPs) form, or a minterm form.

 

 

 

 

 

 

 

3)  For the logic function,  

 

𝑌𝑌 = (𝐴𝐴 + 𝐶𝐶̅)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)

 

 

a)     Develop a truth table for the following standard POS expressions:   

b)     Based on the truth table developed, draw the schematic using NAND gates only 

c)     Based on the truth table developed, draw the schematic using NOR gates only