ECE 3544 Project 3 (Part B) – Design and Synthesis of a Synchronous Finite State Machine Solution

Project 3 (Part B) – Design and Synthesis of a Synchronous Finite State Machine

Read this specification in its entirety before you begin working on the project!

You must do this assignment individually. The following represent unauthorized aids, as the term is used to define cheating in the Virginia Tech Honor System Constitution:
• Using any design element – including Verilog code – from any printed or electronic source other than your course textbook and those sources posted on the course Canvas site.

It is permissible for you to re-use any of your own original Verilog code.


Project Objective
In this project, you will take an existing synchronous finite state machine module and modify it to add features. You will implement your top-level module on the Altera DE1-SoC board, so you will gain practice with assigning pins of your FPGA to the module’s input and output ports, and with synthesizing modules.

Requirements
The DE1-SoC board IS REQUIRED for this project.


Using the Documentation
I have added extensive comments to the modules that you will use as the basis for completing this assignment. You should use these comments in conjunction with the code structures and general code organization to learn more about how to properly formulate state machines in Verilog. Future projects will require you to correctly represent state machines in Verilog; this project represents a good first example of how to do that.

Pay special attention to comments that appear in ALL CAPS. They are meant to draw your attention to particular aspects of the Verilog code. In general, you should remove these comments as a part of documenting the version of the code that you submit.

Study the buttonpressed module to ensure you understand how it operates. Do not modify the buttonpressed state machine. Provide a state diagram that models the behavior of the buttonpressed module in your report. Additionally, provide a timing diagram that demonstrates the timing of pulse_out relative to reset, clock, and button-in. Follow the model provided in the subsequent diagram.



state
pulse_out

Figure 1: Example framework for your timing diagram

From the standpoint of the state machine, the duration of the button press is arbitrary. You should be able to label regions of the row labeled “state” according to the present state of the buttonpressed state machine. Likewise, you should be able identify the value of pulse_out based on the machine state.



Study the fsm16bit module carefully to ensure that you understand how it operates before you make any changes to it.

Project Description
In this assignment, you will design and implement modifications to an existing finite state machine and synthesize it so that it works on the DE1-SoC board. The block diagram shown below represents the top-level module.



Figure 2: Block diagram of the Project 3B top-level module
Take note: The buttonpressed module uses KEY0 as its input to obtain the enable pulse. However, the reset does not also use a buttonpressed module to produce its output. In your report, explain why you think this is the case.

You have been given the basic module; you should implement the changes described in the specification and create a test-bench to simulate your design. Follow the instructions on pin assignment and programming your board to implement the existing behavior of the top-level module on your DE1-SoC board, then test the board to verify that that existing module performs as expected. Do not program your board before you have performed the pin assignment.

Implementing the Basic Module
Make a working folder for this Project and copy the Quartus archive to that folder. You should use the same guidelines for locating and naming your working folder as I have indicated for previous assignments.

Start Quartus. Open the archive file in Quartus. You will find the interface for the project, which already has a basic 16-bit counter. The top-level module already instantiates the buttonpressed and fsm16bit modules. It connects the output of the buttonpressed module to the enable input of the fsm16bit module. Both modules use the FPGA clock as a common clock.

Because the counter is meant to be operated using the board’s pushbuttons, the system is implemented using two communicating state machines. The buttonpressed state machine generates a one clock cycle-wide enable pulse each time the user presses and releases KEY0. The fsm16bit state machine generates the count sequence. The counter is active only on clock cycles when its enable is asserted.

The existing counter will function on the board if you provide instantiations of a correctly-working sevensegment decoder and perform a proper pin assignment. Obtain one of the seven-segment decoder modules that you wrote previously for homework. It should not matter whether you use a version that is modeled using continuous assignment or using procedural assignment. I recommend that you copy it to the working folder for this project and add it to the project. Follow the instructions in the comments of the top-level module to instantiate the seven-segment decoders. Connect the appropriate outputs of the fsm16bit module to the inputs of the corresponding seven-segment decoder.

Pin Assignment
Follow the instructions in the document “Pin Assignment for the DE1-SoC” board to assign pins for the top-level module. Remember that you must perform the analysis and elaboration step on an existing top-level module before you can assign pins for that module, and you must re-compile your project each time you make a change to the pin assignment.

Programming the FPGA with the Basic Module
After you make a complete, correct pin assignment, you can program your board. Follow the instructions in the document “Programming your DE1-SoC Board” to implement the design contained in the top-level module.

After you program your board, test the functionality of the existing design and your board by manipulating the appropriate input switches and pushbuttons and observing the hex displays. You should be able to verify that the design and your board are in working order based on your understanding of the behavior of the top-level module and its instantiated components.

Implementing the Final Design
Modify the fsm16bit module so that it functions as described below. All operations are synchronous and should only occur in conjunction with enable pulses.

It should be clear that the enable input is NOT THE FSM CLOCK. We could design and implement a synchronous FSM that only uses the clock to trigger operations, but we would not be able to see distinct values on the hex displays if they were changing at a rate of fifty million times per second. Therefore, we use the enable to restrict which clock triggers actually cause display changes. In pseudocode:

On a positive clock edge:
If enable = 1
Perform the FSM operation determined by the slide switches.
Else
Leave the counter state unchanged.


System Interface
The system has the following inputs:
• CLOCK_50 (System Clock) – The DE1-SoC board has four 50 MHz clock signals. Use CLOCK_50 as the clock for the sequential elements of your design. Do not use the switches or pushbuttons as clock signals.
• KEY[1] (System Reset) – The Reset button is an active-low system reset. Pressing and releasing the Reset button should return the system to its initial state no matter what its current state.
• KEY[0] (Enable) – The system performs one operation each time KEY0 is pressed and released, in synch with the system clock. Holding enable low does nothing; enable must go low and then high again for the FSM to complete one operation.
• SW[5] (Mode) – If SW5 = 0, the FSM operates as a shift register that performs circular shifts. If SW5 = 1, the FSM operates as a counter.
• SW[4] (Direction) – IF SW4 = 0, the FSM should decrement (count down) if it is in counter mode or shift the FSM state to the right by 1 bit if it is in shift register mode. If SW4 = 1, the FSM should increment (count up) if it is in counter mode or shift the FSM state to the left by 1 bit if it is in shift register mode.
• SW[3:0] (Value) – If the FSM is in counter mode, the value of the counter should increase or decrease by the value given by SW[3:0] These inputs have no function when the FSM is in shift register mode.

The system has the following outputs:
• HEX3, HEX2, HEX1, HEX0 (FSM State) – The hex displays should display the value of the FSM state. Each of the hex displays shows hexadecimal digit that corresponds to four bits of the FSM state.

The inputs check, mode, direction, and value appear in the top-level module provided to you but are unused in the base model of the finite state machine. Part of your task is to incorporate them into the existing FSM module to implement the behavior described above. Update the comments as needed to reflect the changes that you make to the existing counter.

Simulation
The project files include the framework for a test bench. Write your test bench to simulate different operating cases of the counter. A sequence similar to the validation sequence (or the validation sequence itself) would be a good start. The validation test sequences are not nearly exhaustive. While you need not use your test bench to produce an exhaustive set of test results, you should not rely on the validation sequence as the sole test of your system’s correctness.

Follow the instructions in the section of the document entitled “Simulating Quartus Modules Using ModelSim” to simulate the behavior of the top-level module.


Programming the FPGA with the Final Design
After you make sure of your counter’s functionality via simulation, you are ready to program the FPGA with your final design. You should not need to assign the pins a second time, but you might wish to open the Pin Planner to verify that your pin assignment remains unchanged. Follow the instructions in the document “Programming your DE1-SoC Board” to implement the final design on your FPGA.

After your program your board, test the functionality of your final design by manipulating the input switches and observing the LEDs and the hex displays. While the validation sheet contains one sequence of input tests that you can try, the validation test is not exhaustive. As you did with your test bench, you should perform an amount of testing that you consider adequate for verifying the working order of your design.

Project Submission
Write a report describing your design and implementation process. Your report should include waveforms showing the correct behavior of your design.

Your report should include a state diagram that models the buttonpressed module. It should include a timing diagram that shows the clocked behavior of the buttonpressed module. Make sure that your report addresses all other questions asked in the specification.

Additionally, your report should address your conclusions on the proper way to structure finite state machines in Verilog. Use the following questions to guide your discussion:
• Based on the examples of finite state machines presented, how should the procedural blocks representing logic of a synchronous FSM be divided?
• The top-level module contains two different synchronous finite state machines: the buttonpressed module and the fsm16bit module. Do the two modules contain the same number of procedural blocks? If not, how does each module accomplish the functionality of a FSM?
• If there is more than one procedural block involved, in what ways do the blocks differ? What are the responsibilities of each block?


Your project submission on Canvas should include the following items:
1. Project report in PDF
2. The Project 3B Validation Sheet. Put your name and the last four digits of your student number on the Validation Sheet.
3. A Quartus Archive containing the source files for your top-level module, any modules that the top-level module requires to function, and your test benches for the top-level module.
4. Separately, submit the source code files for your top-level module, and any modules that your top-level module requires to function.

To create the Quartus Archive, choose Project > Archive Project after you complete your implementation. When prompted for a name for your archive, the default archive name will be the same as the original archive. Append your Virginia Tech PID to the end of the filename. Make certain that you submit the archive that you create – the one containing your solution to the project – and not the one that I provided to you – the one that only contains the initial files.


Grading for your submission will be as described on the cover sheet included with this description.