Digital_IC-Homework 1: 4-bit Ripple Carry Adder Solved

. Introduction: 

The ripple carry adder (RCA) circuit can be built using a cascade architecture of 1-bit full-adders. As a result, a 4-bit RCA comprises four 1-bit full-adders, which is shown in Fig. 1. In addition, a full-adder can also be constructed by two half-adders and one OR gate. Assume that x and y are 1-bit input signals and s and c are outputs standing for sum and carry. The computation of the half adder can be represented as equation (1). Fig. 2 illustrates the architecture of a half adder and a full adder. In this homework, please design a 4-bit ripple carry adder according to Fig. 1. You are suggested to design the circuit using hierarchy modules including series of half adders and full adders. The values are considered as unsigned integers.

Fig. 1. The architecture of a 4-bit ripple carry adder.

Fig. 2. The architecture of (a) an half-adder and (b) a full adder.

 

s = x⊕y

(1) 

c   = x．y
 

Design Specifications: Block Overview
Fig. 3. The block overview.

I/O Interface
Signal Name
I/O
width
Description
x 
I
4
augend
y 
I
4
summand
c_in 
I
1
carry in
s 
O
4
sum
c_out 
O
1
carry out
 

File Description
File Name
Description
HA.v
The module of half-adder.
FA.v
The module of full adder.
RCA.v
The module of ripple carry adder, which is the top module in this design.
RCA_tb.v
The testbench file. The content in this file is not allowed to be modified.
 

Scoring: Functional Simulation [70%] 
All of the result should be generated correctly, and you will get the following message in ModelSim simulation.

 

Fig. 4. Functional simulation result.

Gate-Level Simulation [30%] Synthesis
Your code should be synthesizable. After it is synthesized in Quartus, a file named RCA.vo will be obtained.

Simulation
All of the result should be generated correctly using RCA.vo, and you will get the following message in ModelSim simulation.

Fig. 5. Gate-level simulation result.

             Device：Cyclone II EP2C70F896C8
 

Submission: Submitted files
You should classify your files into three directories and compress them to .zip format. The naming rule is HW1_studentID_name.zip. If your file is not named according to the naming rule, you will lose five points.

 

 
RTL category
*.v
All of your Verilog RTL code
 
Gate-Level category
*.vo
Gate-Level netlist generated by Quartus
*.sdo
Gate-Level netlist generated by Quartus
 
Documentary category
*.pdf
The report file of your design (in pdf).
             

Report file
Please follow the spec of report. You are asked to describe how the circuit is designed as detailed as possible, and the flow summary result is necessary in the report.

Fig. 6. The flow summary.