CSECS341-Lab 4 MIPS Datapath for R-type Instructions Solved

The objective of this lab is to design a MIPS datapath for R-type instructions (specified in Table 1) as illustrated in Figures 1 to 6.

 

 

 

2      Required Knowledge
•    How to write VHDL code using the behavioral and structural models.

 

 

Figure 1: Top-level block diagram of Datapath 

 

 

 

 

  Dout Dout 

 

 

 

        Figure 2: Program counter register (PC)               Figure 3: Program counter adder (PCADD) 

 

  Dout Dout 

Din Din 

 

 

 

                                 Figure 4: Control                                                              Figure 5: ALU control 

 

•    How to use packages in VHDL.

 

•    How to use the Xilinx Vivado Design Suite to write VHDL code, create block designs, add VHDL modules to block designs and create test benches.

 

 

3      Design
The objective of this lab is to design the MIPS datapath (and control unit) to implement the R-type instructions listed in Table 1. To accomplish this, the following components must first be designed using behavioral VHDL:

 

•    The Program Counter (PC) (Figure 2)

 

•    The Control Unit (Figure 4)

 

•    The ALU Control Unit (Figure 5)

 

•    The PCADD (Figure 3)

 

In addition, a working design for the ALU, Register-File and Instruction Memory are provided on the Beachboard. You will have to modify the provided ALU to add the functionality for the slt instruction. The provided Register-File and Instruction memory units must be used as they are pre-loaded with initial values and the test program, respectively.

The datapath should be designed as a block design. Figure 6 illustrates the connections between the components. Table 2 includes all the components that must be designed, as well as the datapath, and the method by which the design is to be implemented.

   

Figure 6: Datapath for R-type instructions 

Table 1: R-type instructions to implement
No 
Operation 
Mnemonic 
Opcodehex 
Functionhex 
1 
Add 
add 
00 
20 
2 
Add unsigned 
addu 
00 
21 
3 
Subract 
sub 
00 
22 
4 
Subract unsigned 
subu 
00 
23 
5 
And 
and 
00 
24 
6 
Or 
or 
00 
25 
7 
Xor 
xor 
00 
26 
8 
Nor 
nor 
00 
27 
9 
Set less than 
slt 
00 
2A 
10 
Set less than unsigned 
sltu 
00 
2B 
           

*For splitting a bus into smaller width buses, use the Slice IP. 

*Use the specified names for both file and input and output ports in case of datapath.  

4     Testing 
The registers in the register file are initialized to values shown in Table 3. The instruction memory contains the test program which is shown in below. Calculate the final values of the registers after the completion of the execution of the test program and complete Table 3.

Table 2: Components to design
No 
Component 
VHDL model 
Design model 
1 
PC 
Behavioral 
HDL 
2 
PCADD 
Behavioral 
HDL 
3 
Control Unit 
Behavioral 
HDL 
4 
ALU Control Unit 
Behavioral 
HDL 
5 
Datapath 
- 
Block Design 
 

 

Build a testbench with a clock period of 20ns and run the simulation for 1 clock cycles with reset=’1’ and for 10 clock cycles with reset=’0’. Compare the final values of the registers from the simulation with the values you calculated in Table 3.