In this project, you will use Altera Quartus II with Verilog. You will the 32-bit MIPS processor. The block that you will design will get no inputs from outside. You will have two memories: Data Memory and Instruction Memory. The instructions must be loaded to the instruction memory and the data must be in data memory. You will support xor, xori, slt, sltiu, lw, lh, lb, sw, sb, j, jal, jr, beq, bne, add, sub, and, or, sra, srl, sll, sltu and addi, addiu, andi, ori, slti, lui instructions. Insert two new instructions on your own to MIPS. Find two suitable new instructions on your own, define them and design them.
You will write test bench and simulate your design for verification. You will write the register and memory contents before and after the execution of instructions using writememh in your test bench verilog code. You will initialize memory contents using readmemh.
The data memory size will be 128KB whereas the instruction memory size will be 32KB. Remember that addressing for a 128KB memory only requires 17 bits instead of 32 bits in regular MIPS. Update your design accordingly.
