CSCE312 Project 3- Sequential Chips Solution

Grading
(A) Project Demo 
You will be graded for correctness of the chips (hdl) you have designed and coded. So, make sure to test and verify your codes before finally submitting on eCampus.
Rubric: Each circuit needs to pass all its test cases to get the points, else you will receive a
0 on that circuit.

The questions can involve drawing circuit diagram of randomly selected chips. Should not be difficult for you if you have understood the core inner workings of your project.

Deliverables & Submission
You need to turn in the completed HDL files for all the chips.
Put your full name in the introductory comment present in each HDL code.
Use relevant code comments and indentation in your code.
Zip all the required HDL files into a compressed file FirstName-LastName-UIN.zip Submit this zip file on eCampus.











Background

The computer's main memory, also known as Random Access Memory (RAM), is an addressable sequence of n-bit registers, each designed to hold an n-bit value. In this project you will gradually build a RAM module. This involves two main issues: (i) how to use gate logic to store bits persistently, over time, and (ii) how to use gate logic to locate ("address") the memory register on which we wish to operate. In addition, you will build functions that are constructed with combinational and sequential logic design elements.

Objective
Build all the chips described in the list below. The only building blocks that you can use are primitive DFF gates to start with, and subsequently chips that you will build on top of them, and chips described in earlier projects.

Chips
Chips Name: Description File Name
Bit 1-bit register (use DFF) Bit.hdl
Register 16-bit register Register.hdl
RAM8 8 16-bit register memory RAM8.hdl
RAM64 64 16-bit register memory RAM64.hdl
RAM512 512 16-bit register memory RAM512.hdl
PC 16-bit program counter PC.hdl
Aggie Cipher 4-bit counter using D flip flop AggieCipher.hdl
Fibonacci Fibonacci Sequence generator Fibonacci.hdl


Aggie Cipher

out=in+counter, where counter={0,1,2,3,4,5,6,....,15,0,1,2,.....}


Fibonacci Sequence generator:
The general Fibonacci sequence is a sequence that starts with f0=0 and f1=1 . The next number in the sequence is the sum of the previous two numbers. So the Fibonacci number sequence generated in our circuit will be: 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89…



To use this circuit, you have to control these signals, namely, enable1, enable2, enable3 and msel.

● msel=0 will select the starting values f0 and f1 of the Fibonacci Sequence
● msel=1 will keep running the Fibonacci sequence with sum(t+1) ← sum(t) + sum(t-1) for clock cycle t
● enable1=1 or enable2=1 or enable3=1 activate respective registers by loading the corresponding input values to corresponding register outputs
● enable1=0 or enable2=0 or enable3=0 retain the register outputs from the previous cycle

The test file Fibonacci.tst assigns the values to these control signals.
See how output in the Fibonacci.out file changes while changing those signals.

For each chip, we supply a skeletal .hdl file with a missing implementation part.

In addition, for each chip from Bit till PC we supply a .tst script that instructs the hardware simulator how to test it, and .cmp ("compare file") containing the correct output that this test should generate.
For Aggie Cipher and Fibonacci, we provide incomplete .tst files.

Your task is to complete and test the supplied skeletal .hdl files while also completing the .tst files for AggieCipher and Fibonacci Contract
When loaded into the supplied Hardware Simulator, your chip design (modified .hdl program), tested on the supplied .tst script, must produce the outputs listed in the supplied .cmp file. If that is not the case, the simulator will let you know.


Resources
The relevant reading for this project is
Chapter 3 https://docs.wixstatic.com/ugd/44046b_1801b5682e4d4a67bd05e14235665d8b.pdf
Appendix A https://docs.wixstatic.com/ugd/44046b_d715f80dca2a43af926131a52e3d3d90.pd f

Specifically, all the chips described in Chapter 3 should be implemented in the Hardware Description Language (HDL) specified in Appendix A.

The resources that you need for this project are the supplied Hardware Simulator and the files listed above. Download your hdl files from ecampus and replace these files to those stored in your projects/03 directory.

Tips
The Data Flip-Flop (DFF) gate is considered primitive and thus there is no need to build it: when the simulator encounters a DFF chip part in an HDL program, it automatically invokes the built-in tools/builtInChips/DFF.hdl implementation.


Tools
Following is a screenshot of testing a built-in RAM8.hdl chip implementation on the Hardware Simulator: