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CSC342_343 - MIDTERM Lab Project - Assignment 1   - Solved

 based on Tutorial
“Laboratory Exercise Tutorial  Memory blocks using VHDL array and LPM modules.” DESIGN MEMORY AS A VHDL ARRAY AS SHOWN IN PART III, and using LPM SRAM modules. 

o   Design 32 bit word  Data Memory module based on LPM tutorial attached. Data memory size 16 words. 

o   Design 32 bit word  INSTRUCTION Memory module based on LPM tutorial attached. Instruction memory size 32 words. 

o   Design 32 bit  register DUAL PORTED REGISTER FILE  module based on 2-port RAM  LPM tutorial attached. EACH register is 32 bits. 



 

•        3.. Archived Project files with readme  

• Assignment 2 based on Intel AP note
“USING LIBRARY MODULES IN VHDL DESIGNS” 

Design 32 bit  ADD/SUB unit as described in the second attached tutorial. 

  You have to create two versions: 

•       From scratch and  

•       Another one using LPM modules.  

•       You have to load data to ADD/SUB unit from DATA memory (just copy NOT TO USE LOAD INSTRUCTION) USE MIF file to load data to memory.

•       You have to design circuit to output N – negative flag, Z- zero flag, O -overflow flag.

•       Demonstrate operation using waveforms.

•       Demonstration of ACCUMULATOR  unit for ADD and for SUB.

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