CSC21100 - Project 04 - Solved

 Naming convention:

Report: “FirstName_LastName_Project_XX_CCY.pdf”*

Project: “FirstName_LastName_Project_XX_CCY.zip”*

*Replace “XX” and “Y” with the actual project number (two digits) and section number, respectively.  

5.     After the due day, all submissions are final. You cannot change it for any reasons. Double check before you make the submission.  

 
 

In this project, students are expected to use the Xilinx ISE Design Suite (Webpack edition) 14.7 to complete the following tasks.

 

Please read the instructions carefully. Failing to follow the instructions would lead to significant point deductions.

 

Task 1: S′-R′ Latch (5 points)
 

An S′-R′ latch operates according to the following function table.  

 

  

 

Write a VHDL program to implement an S′-R′ latch using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.  

 

  

 

Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.

 

 

 

Requirement(s): 

(1)   You must follow the structural design method. 

(2)   You must follow the submission guidelines.

 

Note: no points will be given if any of the requirements are not satisfied.

 


 

1.1
Draw a circuit diagram of the module to show the design. Use your own language to describe the function of the module to be implemented in VHDL. (1 point) 
1.2
Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point) 
1.3
Show simulation results (e.g. the waveforms). Describe the outcome of each testcase with screenshots. Explain why the simulation result is correct. (1 point) 
 


 

1.4
Can compile without any errors. (1 point) 
1.5 
Can run simulations without any errors. (1 point) 
 

 

 

Task 2: S-R Latch with enable (5 points)
 

An S-R latch with enable operates according to the following function table.  

 

  

 

It can be built based on a S′-R′ Latch. Write a VHDL program to implement the SR Latch with Enable using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.

 

    

Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.

 

 

 

Requirement(s): 

(1)   You must follow the structural design method. 

(2)   You must use the module(s) implemented before.

(3)   You must follow the submission guidelines.

 

Note: no points will be given if any of the requirements are not satisfied.

 

)
 

2.1
Draw a circuit diagram of the module to show the design. Use your own language to describe the function of the module to be implemented in VHDL. (1 point) 
2.2
Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point) 
2.3
Show simulation results (e.g. the waveforms). Describe the outcome of each testcase with screenshots. Explain why the simulation result is correct. (1 point) 
 


 

2.4
Can compile without any errors. (1 point) 
2.5 
Can run simulations without any errors. (1 point) 
 

 

Task 3: D-Latch (5 points)
 

Build a D latch in Xilinx according to the following function table.

 

  

 

The D latch can be built based on an S-R Latch with Enable. Write a VHDL program to implement the D latch using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.

 

  

 

Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.

 

 

Requirement(s): 

(1)   You must follow the structural design method. 

(2)   You must use the module(s) implemented before.

(3)   You must follow the submission guidelines.

 

Note: no points will be given if any of the requirements are not satisfied.

 

 

3.1
Draw a circuit diagram of the module to show the design. Use your own language to describe the function of the module to be implemented in VHDL. (1 point) 
3.2
Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point) 
3.3
Show simulation results (e.g. the waveforms). Describe the outcome of each testcase with screenshots. Explain why the simulation result is correct. (1 point) 
 


 

3.4
Can compile without any errors. (1 point) 
3.5 
Can run simulations without any errors. (1 point) 
 

 

Task 4: Negative Edge Triggered D Flip-Flop (5 points)
 

Build a negative edge triggered D flip-flop in Xilinx according to the following function table.

 

   

 

The negative edge triggered D flip-flop can be built based on the D latch in the previous task. Write a VHDL program to implement the negative edge triggered D flip-flop using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.

 

  

 

Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.