Naming convention:
Report: “FirstName_LastName_Project_XX_CCY.pdf”*
Project: “FirstName_LastName_Project_XX_CCY.zip”*
*Replace “XX” and “Y” with the actual project number (two digits) and section number, respectively.
In this project, students are expected to use the Xilinx ISE Design Suite (Webpack edition) 14.7 to complete the following tasks
Finite State Machine (FSM)
Write a VHDL program to implement a “combination lock” state machine that activates and “unlock” output when a certain binary input sequence is received.
Requirements:
• Similar to the example in the lecture, the FSM has one input X and two outputs UNLK and HINT;
• The UNLK output should be 1 if and only if X is 1 and the sequence of inputs received on X at the preceding three clock ticks was “101”, and the FSM returns to the INIT state;
• HINT output should be 1 if and only if the current value of X is the correct one to move the machine closer to being in the “unlocked” state (with UNLK=1);
• Whenever a wrong input is detected, the FSM returns to the INIT state and HINT=0;
• For the state memory, only two D flip-flops are allowed;
In this task, use the FD component (essentially a D flip-flop) defined in the UNISIM library. In order to use the FD component, please make sure you have the following lines in your VHDL program to include the UNISIM library.
Then you will need to declare the component in the VDHL architecture definition. For example:
Then you can use it like this:
Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.
Note: no points will be given if any of the requirements are not satisfied.
