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CSc 21100 Project 03 Solved
CSc 21100
Project 03
(20 points)
IMPORTANT!
Please follow the submission guidelines below or your submission will be rejected.
1. You are expected to submit two files (a PDF lab report and a ZIP file containing the source files) to Blackboard. Note that both files must be upload in the same submission attempt.
2. Each task must have its own source file(s). For VHDL assignments, all source files of this assignment must be in a single Xilinx VHDL project.
3. For VHDL assignments, you must use the export function of the Xilinx ISE Design Suite to create the ZIP file properly. Please refer to Blackboard - Content - Assignments - Exporting_VHDL_project_files
4. Naming convention:
Report: “FirstName_LastName_Project_XX_CCY.pdf”*
Project: “FirstName_LastName_Project_XX_CCY.zip”*
*Replace “XX” and “Y” with the actual project number (two digits) and section number, respectively.
5. After the due day, all submissions are final. You cannot change it for any reasons. Double check before you make the submission.
In this project, students are expected to use the Xilinx ISE Design Suite (Webpack edition) 14.7 to complete the following tasks.
Please read the instructions carefully. Failing to follow the instructions would lead to significant point deductions.
Task 1: 2-to-4 Decoder (5 points)
A 2-to-4 decoder operates according to the following function table.
Implement a 2-to-4 decoder in VHDL using structural design: Please adopt the following as the entity declaration.
Note that, many logic gates are defined in the UNISIM library. In order to use these gates, you need to add the following lines in your VHDL program to include the UNISIM library.
Write a test-bench program and run simulations to validate your design: Use the given test cases below in your test-bench program. Pay attention to the signal names, signal values, and the time.
Deliverable(s):
Requirement(s):
(1) You must follow the structural design method.
(2) You must follow the submission guidelines.
Note: no points will be given if any of the requirements are not satisfied.
Rubric (Report)
1.1. Use your own language to describe the function of the module to be implemented in VHDL. (1 point)
1.2. Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)
1.3. Show simulation results (e.g. the waveforms). Explain the outcome of each test case with screenshots. Show why the simulation result is correct. (1 point)
Rubric (Source Code)
1.4. Can compile without any errors. (1 point)
1.5. Can run simulations without any errors. (1 point)
Task 2: 3-to-8 Decoder (7 points)
Implement a 3-to-8 decoder using the 2-to-4 decoder you have implemented in Task 1. The input to the 3-to-8 decoder should be labeled as A. It needs to be a 3bit bus. The output should be labeled as O, which is an 8-bit bus. Please use the following entity declaration for the 3-to-8 decoder.
Note that: (1) please adopt the structural design approach; (2) in addition to the 2to-4 decoders, you also need to include some logic gates to make it work.
In order to use the 2-to-4 decoder from Task 1, you will need to declare the 2-to-4 decoder as a component in the VDHL architecture definition of the 3-to-8 decoder:
Then you can use the decoder like this:
Once you successfully completed the implementation of the VHDL module, write a test-bench program and run simulations to validate your design. Use the given test cases below in your test-bench program. Pay attention to the signal names, signal values, and the time.
Deliverable(s):
Requirement(s):
(1) You must follow the structural design method.
(2) You must use the module(s) implemented before.
(3) You must follow the submission guidelines.
Note: no points will be given if any of the requirements are not satisfied.
Rubric (Report)
2.1 Use your own language to describe the function of the module to be implemented in VHDL. (1 point)
2.2 Draw a circuit diagram of the module to show the design. (1 point)
2.3 Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)
2.4 Show simulation results (e.g. the waveforms). Use the simulation results to explain why the implemented circuit is working correctly. (2 points)
Rubric (Source Code)
2.5 Can compile without any errors. (1 point)
2.6 Can run simulations without any errors. (1 point)
Task 3: A 4-bit Ripple Adder (8 points)
Implement a 4-bit ripple adder, similar to the one we discussed in class. You need to first implement a 1-bit full adder then cascade them to build the 4-bit ripple adder. Please use the following entity declarations for the 1-bit full adder and the 4-bit ripple adder.
Note that: (1) please adopt the structural design approach; (2) please make sure you use the following libraries and packages:
In order to use the 1-bit full adder, you will need to declare it as a component in 4bit ripple adder implementation:
Then you can use the 1-bit full adder like this:
Once you successfully completed the implementation of the VHDL module, use the test-bench program below and run simulations to validate your design.
Deliverable(s):
Requirement(s):
(1) You must follow the structural design method.
(2) You must use the module(s) implemented before.
(3) You must follow the submission guidelines.
Note: no points will be given if any of the requirements are not satisfied.
Rubric (Report)
3.1 Use your own language to describe the function of the module to be implemented in VHDL. (1 point)
3.2 Draw a circuit diagram of the module to show the design. (1 point)
3.3 Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)
3.4 Show simulation results (e.g. the waveforms). Use the simulation results to explain why the implemented circuit is working correctly. (3 points)
Rubric (Source Code)
3.5 Can compile without any errors. (1 point)
3.6 Can run simulations without any errors. (1 point)
