CS410001-Project 1 Solved

a. Architecture Design:

•           Refer to textbook Chapter 2 “Instructions” and Chapter 4.1~4.4 “The Processor”.

•           The executable file should be named “single_cycle” and take no command-line arguments.  

•           All registers, except PC and $sp, are initialized to 0’s.

•           Assume that the instruction memory is of 1K bytes size and all contents are initialized to 0’s.

•           The data memory is of 1K bytes size and the memory contents are initialized to 0’s.  

•           Your test case should run no more than 500,000 cycles.  

 

b. Instruction Set:

•           Implement all the instructions specified in the reduced MIPS R3000 ISA in Appendix A, “Datasheet for the Reduced MIPS R3000 ISA”.  

•           The execution of the single-cycle processor simulator should terminate after executing the “halt” instruction.

 

c. Input Test Case File and Format:

                    •     Design your own test case by providing the following two binary files:

                              1.    iimage.bin:  

a.         This file specifies the instruction image (in big-endian format, encoded in binary).  

b.         The first four bytes indicate the initial value of PC, i.e. the starting address to load the instruction image.  

c.         The next four bytes specify the number of words to be loaded into instruction memory.

d.         The remaining are the program instructions to be loaded into I-memory.  

                              2.    dimage.bin:  

a.         This file specifies the data image (in big-endian format, encoded in binary).  

b.         The first four bytes indicate the initial value of $sp.  

c.         The next four bytes specify the number of words to be loaded into data memory, starting from address 0.  

•           For format details, please refer to Appendix B, “Input Samples”.  

•           Place both “iimage.bin” and “dimage.bin” under a folder named testcase/ at the same directory where your executable file resides.

•           We will pool all test cases from the class to evaluate everyone’s simulator. Your (valid) test case gets higher grade if more simulators failed running your test case.  

 

d. Output File and Format:

                    •     For each test case, generate the following two output files:

1.         snapshot.rpt: Record all the register values at each cycle.

2.         error_dump.rpt: Record any error messages.   

•           Place the output files at the same directory where your executable file resides.

•           For details, please refer to Appendix C-1, “Output Samples for Project 1” and Appendix D, “Error Detection Samples”.

 

e. Modularized implementation

• Suggest that you should modularize your simulator implementation based on processor architecture. For example, this is a possible program structure:

a.      simulator.c      // Define simulator behaviors and main function

b.     instruction.c    // Define & decode instructions

c.      regfile.c                       // Register function

d.     memory.c        // Memory function (for both instruction & data memories)

e.      etc.c……                     // other miscellaneous functions

• Appropriate header file or object-oriented programming format are also highly recommended design pattern.