Objective: The main purpose of this lab, along with the succeeding one, is to acquaint you with RTL programming, specifically Verilog. These initial steps aim to equip you with a strong foundation in Verilog, setting the stage for more advanced labs ahead. Description: This lab involves the implementation of a variety of basic hardware modules using Verilog. In addition, you will be tasked with developing the requisite testbench code to verify the correctness of your modules. This dual approach not only provides hands-on experience with Verilog but also emphasizes the importance of testing and validation in hardware design. 1. Included modules: a. Combinational Circuits; b. Vector Signals; c. Module Hierarchy; d. Always Block & Sequential Circuits 2. Specification about each modules: 3. Combinational Circuits 4. Vector Signals 5. Module Hierarchy 6. Always Block & Sequential Circuits 7. Finite State Machine Submission Format: 1. We use Gradescope for the code submission and grading. 2. Please submit the completed "submission.v" file for each module to the corresponding assignment in Gradescope. DO NOT CHANGE THE FILENAME AND MODULENAME! 1. If you pass the test cases. 2. Note: All test cases are randomly generated for all modules. 3. Partial grading Policy: Only module 3 has partial grading, where there is a checkpoint for the submodule design. FAQ: [Q] How to debug the code? [A] The gradescope will provide the input and output for both your code and the golden code if the test failed. You can compare the output to debug your code. Additionally, writing testbench is an important skill in processor design, you can also design your own testbench and install iverilog on your computer to debug the code. [Q] Any online tutorials to watch? [A] link1: Focus on the concept and programing as we will use different devices link2: modelsim (similar to vivado xsim) link3, link4: more comprehensive digital design and RTL programing tutorial videos
