CS224-Lab 5 Implementing the MIPS Processor with Pipelined Microarchitecture Solved

·       Answer the questions given in Part 1)a-f in a PDF report. Give your test codes in this report as well. If you need to explain your modifications in the processor, you can do in the report as well.

·       You will modify the given System Verilog Skeleton code to reflect the changes asked in Part 1-f. Put this in a TXT file for submission to MOSS testing.

·       You will create programs to test your processor as outlined in Part 1-e. Submit these assembly instructions both in yout PDF and TXT files. This will be used to test your Processor with the modifications you made. Submit this as part of the code. The best way to put assembly codes in your submission would be to put the HEX instructions and after each line you can add a comment to indicate the corresponding assembly instruction.

 

OPTIONAL (PART 2)

·       You may simulate/synthesize and test it on Vivado if your modified processor properly executes all the instructions.

·       Testbench

 

Purpose: In this lab you will implement and test a pipelined MIPS processor using the digital design engineering tools (System Verilog HDL, Xilinx Vivado).  To do this, you will need to add pipeline registers, forwarding MUXes, a hazard unit, etc. to your datapath, and of course make the control pipelined as well.  You will be provided a skeleton System Verilog code for the Pipelined MIPS processor and fill the necessary parts to make it work. 

 

Summary 

Part 1 Design Report: Pipeline hazards evaluation and preparing test modules in MIPS.

 

Part 1. Design Report 

 

At the end of this lab, you will have implemented the pipelined MIPS architecture that can be seen in the file that is provided as PipelineDatapath.PNG (Notice that there is no early branch prediction in this pipeline. Hence, the branch resolution is done in the Decode stage.). Note also that there is no jump instruction implemented as well. Your Design Report should contain the following items along with code 

b) The list of all hazards that can occur in this pipeline.  For each hazard, give its type (data or control), its specific name (“compute-use” “load-use”, “load-store”, “branch” etc.), the pipeline stages that are affected.

c) For each hazard, give the solution (forwarding, stalling, flushing, combination of these), and explanation of what, when, how.

dThe logic equations for each signal output by the hazard unit, as a function of the input signals that come to the hazard unit.  This hazard unit should handle all the data and control hazards that can occur in your pipeline (listed in b) so that your pipelined processor computes correctly.

e) Write small test programs, in MIPS assembly, that will show whether the pipelined processor is working or not.  Each of your test programs should be designed to catch problems, if there are any, in the execution of MIPS instructions in your pipelined machine. Write:

A test program with no hazards (to verify that there are no problems with the connections in your pipeline etc.)
A test program that has one type of hazard, and another, and another...
In the end, have at least 4 test programs (testing at least 3 hazards) with their machine code (in hex).

You can use the student-written assembler tool available online to help you quickly implement your test programs[1].  Remember that the goal of testing is to verify that all the instructions are fully working, and that all the instructions are working even in the presence of hazards.

f) You are given a skeleton System Verilog code for your pipelined MIPS processor in the file PipelinedMIPSProcessorToFill.txt. The places in the code that needs to be modified are shown with comment blocks above them. Fill them to implement Pipelined Processor. You don’t need to follow the skeleton code point by point. If you think your design is better, you are welcome to try it in your code, as long as your version of the code works, too. 

Part 2:  Implementation and Simulation (Optional)

a) Now make a System Verilog testbench file and using Xilinx Vivado, simulate your Pipeline Processor by executing the test programs you wrote at Prelim e). Implement a new top module in order to see memwrite, regwrite, writedata, pc, instruction and resultw signals. Study the results given in the simulation window.  Find each instruction, and understand its values. Do this step for each of the test programs you wrote.  

b) When you have integrated all the System Verilog modules together and your whole pipelined MIPS is working in simulation with the test programs you wrote,.