CS223-Lab 2 Full adder, Full Subtractor and 2-bit Adder on FPGA Solved

In the previous lab, you implemented half adder and subtractor using gates on the bread board. In this lab you will implement very similar circuits, but this time on FPGA. Today's lab needs considerable advance preparation. You need to learn how to work with Xilinx’s design tool set before attending the lab. In addition, SystemVerilog models and testbenches should be prepared in advance, and assembled neatly into a Preliminary Report with a cover page and pages for the SystemVerilog codes. Each page should have a proper heading. The report should be uploaded on Moodle as a pdf file before the start of the lab. The content of the report will be as follows:

(a)  A cover page including: course code, course name and section, the number of the lab, your name-surname, student ID, date.

(b)  Circuit schematic for a 2-bit adder made from two full adders shown in Figure 1. (use full adders as black-boxes, you don’t need to draw the logic diagram of full adder again).

(c)   Behavioral SystemVerilog module for the full adder.

(d)  Structural SystemVerilog module for the full adder and a testbench for it.

(e)   Structural SystemVerilog module for the full subtractor and a testbench for it (refer to Figure 3).

(f)   Structural SystemVerilog module for the 2-bit adder and a testbench for it. Use the full adder module you wrote in part (c).

Note that behavioral model describes the function of a module using Boolean equations and continuous assignment statements; whereas structural modeling refers to using and combining simpler pieces of modules (it is an application of hierarchy). You can refer to Chapter 4 of your textbook and slides of Chapter 4 on Moodle while preparing your modules and testbenches.

Additional pre-lab work: 

You should read the following documents (available on Moodle) to be familiar with steps of design flow (Simulation, Synthesis, Implementation, Bitstream Generation, Downloading to FPGA board), using Xilinx Vivado tool. You can download, install and practice working with Xilinx Vivado on your own computer with free WebPACK license. Currently, Mac is not supported by Vivado, so if you are a Mac user, you would need to set up a virtual machine in order to use Vivado. Less ideal and a temporary solution would be to use the following site, but you will not be able to generate bitstream and program your FPGA:  Suggestions for Lab Success.

•        Basys 3 Vivado Decoder Tutorial.

•        Vivado Tutorial.

•        Basys 3 FPGA Board Reference Manual.

  

Figure 1: Full Adder 

 

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Figure 2: Truth table of the full adder 

 

 

  

Figure 3: Full Subtractor 

 

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Figure 4: Truth table of the full subtractor 

Implementation on FPGA
In this step, you implement your modules on FPGA board. You don’t need to connect your Basys 3 board to the Beti board. Working with standalone Basys 3 and having it connected to your computer is enough for this lab. There are some switches and LEDs available on Basys 3 which you can use them.  Create a new Xilinx Vivado Project. Use appropriate names for files and folders, keeping the project in a directory where you can find it later and erase it (at the end of lab).

(a)  Simulation: Implement the full adder module in behavioral style (preliminary part-c). Then, using the SystemVerilog testbench code you wrote, verify in simulation that your circuit works correctly.

(b)  Simulation: Implement the full adder module in structural style (preliminary part-d). Then, using the SystemVerilog testbench code you wrote, verify in simulation that your circuit works correctly.

(c)   Simulation: Implement the full subtractor module in structural style (preliminary part-e). Then, using the SystemVerilog testbench code you wrote, verify in simulation that your circuit works correctly.

(d)  Simulation: Implement the 2-bit adder module using two full adders you wrote (preliminary part-f). Then, using the SystemVerilog testbench code you wrote, verify in simulation that your circuit works correctly.

(e)   When you are convinced that your codes work correctly,. Be prepared to answer questions that you may be asked.

(f)   Program the FPGA: Now, follow the Xilinx Vivado design flow to synthesize, implement, generate bitstream file, and program all three modules to Basys 3 FPGA board.

(g)  Test your design: Using the switches and LEDs (on Basys 3) that you have assigned in constraint file (.xdc), test your designs. When you are convinced that they work correctly, Be prepared to answer questions that you may be asked.