Combinational Chips (Arithmetic+ALU)
Objective:
Build the gates described in Chapter 2 (see table below), which will test your understanding of Boolean Logic and Arithmetic, building the gates that do so.
What do you turn in?
What do you turn in?
A Word document (or PDF) with screen shots of each of the working (or not) logic gates. You should also upload the documentation.pdf file (see Documentation Instructions for guidelines on how to do this) per Project Submission Guidelines.
NOTE: the HDL code you write for the ALU (ALU.hdl) will be used in BOTH test scripts (ALU-nostat.tst and ALU.tst). Please take a screen shot of the output from both tests. This is to maximize partial credit for you in case you aren’t able to get the status output flags working.
Chip
Working?
Well built?
HalfAdder
/
10
/
5
FullAdder
/
10
/
5
Add16
/
10
/
5
Inc16
/
10
/
5
ALU + no status
outputs (ALU-
nostat.tst)
/
15
/
5
ALU + full test (ALU.tst)
/
5
/
5
Subtotal
/
60
/
30
Documentation
/
10
See http://nand2tetris.org/02.php for some tips/resources/tools (note that the assignment on the website is substantially different from the assignment that is described above, if you need clarification email your instructor. You will be graded based on this documents requirements).
