Objective: Build all gates described in Chapter 3 (see table below), which will test your understanding of sequential chips for our HACK architecture.
Grading method: If the chip passes all the tests specified in the supplied test script, it receives 60% of the grade. 30% goes to it being well built (the lowest number of chips to implement), with the remaining 10% going towards documentation provided for each chip. Generally speaking, we prefer implementations that use as few chip parts as possible, even if it implies a less efficient chip design (in term of # of AND/OR/NOT chips). Higher-level chips are considered as one chip part (ex. Mux, DMux, Or8Way, etc.)
What do you turn in? A Word document (or PDF) with screen shots of each of the working (or not) logic gates. You should also upload the documentation.pdf file (see Documentation Instructions for guidelines on how to do this) per Project Submission Guidelines.
