For this lab, and the rest of the class, you will need to familiarize yourself CircuitSim. To do so, you can follow the following tutorial and implement it in the tutorial.sim file using CircuitSim
•
Implement the logic as described in the above link in the corresponding circuit. Note that this will not be corrected by the autograder and is for your practice only.
1 OR Gates
1.1 What is an OR Gate
• OR
(A|B)
A
B
(A|B)
0
0
0
0
1
1
1
0
1
1
1
1
• NOR
∼ (A|B)
A
B
∼ (A|B)
0
0
1
0
1
0
1
0
0
1
1
0
1
• NOT
(∼ A)
A
(∼ A)
0
1
1
0
1.2 Building an OR Gate
• Now that you know what the truth table of an OR gate is, lets try to build one in the transistors subcircuit of the labs.sim file.
• Since we are using CMOS gate design, we will need a pair of p-type transistors and a pair of n-type transistors to build a NOR gate.
• We will then need one of each of the p-type transistors and n-type transistors to build a NOT gate which we will add to the end of our NOR gate.
• Remember that due to some laws of physics, our p-type transistors will need to be connected to Vdd and our n-type transistors need to be connected to ground.
• Since we want the output to be low for our NOR gate when A or B or both are high, we will need to put our p-type transistors in series so that power does not flow to the output when either is on.
• Because we are using CMOS logic, we know that to complement our p-type transistors being in series, we need to connect our n-type transistors in parallel to the ground.
• Play around with the settings for the transistors until you have a working NOR Gate.
• Now you can use one p-type and one n-type transistor in series to negate the output of our NOR gate, by passing the output to both the transistors and getting the final output from the wire connecting them, making it an OR gate.
• Note: You are only allowed to use the elements in the wiring tab of CircuitSim for this subcircuit. Do not use elements in the gates tab of CircuitSim.
2 Synthesizing Logic
2.1 ANDs, ORs and DeMorgan’s Law
In this section you will be synthesizing a logical statement into gates for testing. This circuit must be made in the deMorgan subcircuit of the lab.sim file. Feel free to use the pre-made gates in the gates tab of CircuitSim.
• Logic: (∼ (∼ A&B)| ∼ (∼ B|C))
See the corresponding circuits and implement the logic as described above. Do not change the names of the inputs or outputs. If you do, our little autograder will cry!!
