CS2100 Tutorial 4 Solved

 

1.      Given below are the contents of some registers and memory locations, where mem(A) refers to the data word stored in the memory location at address A:

                 $s0 =  100
mem (100)      =   1000
                 $s1 =  160
mem (160)      =   1600
                 $s2 = 200
mem (200)      =   2000
                $s3  =  240
mem (240)      =   2400
                 $s4 =  300
mem (300)      =   3000
                 $t0 =  10000
mem (10000) =   100
                 $t1 =  15000
mem (15000) =   150
                  $t2 = 20000
mem (20000) =   200
                  $t3 = 25000
mem (25000) =   250
                  $t4 = 30000
mem (30000) =   300
 For each of the MIPS instructions below, ‘op’ is an unknown opcode, which is not of our concern here. For each of the data operands in the instruction, if the format is legal, give its memory address (if applicable) and the content inside. Note that $s0, …, $s4, $t1, …, $t4 are symbolic register names, $zero is register 0 with content zero inside, and only the three addressing modes (register, immediate, and displacement) mentioned in class are considered as legal.

(a)         op $t1, $t2

(b)         op $s2, 100($zero)       (c) op $t4, 40($s2)

(d)      op $s3, 200($zero)

(e)      op $t3, $zero($t1)

(f)       op $s1, 140($s1)

       The answers for (a) have been done for you.

 
Operand 
Target Memory Address 
Content 
(a) 
$t1 

$t2 
Not applicable 

Not applicable 
15000 

20000 
(b) 
$s2 

100($zero) 
 
 
(c) 
$t4 

40($s2) 
 
 
(d) 
$s3 

200($zero) 
 
 
(e) 
$t3 

$zero($t1) 
 
 
(f) 
$s1 

140($s1) 
 
 
             

 

For question 2 below, we are exploring four different types of ISAs. MIPS belongs to the Register-Register style.

2.      You are tasked to design a dedicated 16-bit processor to perform simple addition and would like to evaluate the design using the four different instruction set architecture (ISA) styles.  For each of these architectures, the corresponding data movement and arithmetic operations are shown below.  Note that the operands for the instructions are annotated with either @ for address, or $ for register.

ISA
Instructions
Explanation
Stack 
push @src pop @dest add 
Load value in @src onto top of stack. 

Transfer value at top of stack to @dest. 

Remove top two values in stack, add them, and load the sum onto top of stack. 
Accumulator
load @src

add @src

 

store @dest 
Load value in @src into accumulator. Add value in @src and value in accumulator, and put sum back into accumulator. 

Store the value in accumulator into @dest. 
Memory-Memory 
add @dest, @src1, @src2 
Add values in @src1 and @src2, and put the sum into @dest. 
Register-Register 
load $reg, @src add $dest, $src1, $src2

 

store $reg, @dest 
Load value in @src into $reg. 

Add values in $src1 and $src2, and put sum into $dest. 

Store value in $reg into @dest. 
Consider the following three C statements with integer variables a0, a1 and a2:

     a0 = a1 + a2;       a1 = a0 + a2;   a2 = a0 + a1; 

For each of the four architectural styles above, write the assembly code corresponding to the above C code.  Assume that the values of a0, a1, a2 are pre-assigned to memory in addresses @a0, @a1, @a2 respectively. The registers are denoted by $r0 to $r4. First part of each code is given.

Stack 
Accumulator 
Memory-Memory 
Register-Register 
push @a1 push @a2 

add 

 
load @a1

add @a2

 
add @a0, @a1, @a2

 
load $r1, @a1

 
 

3.      This is a follow up on question 2. We studied the assembly code generated for four different storage architectures, namely stack, accumulator, memory-memory and register-register. For your reference, the code fragment corresponds to the following high level statements:

     a0 = a1 + a2;       a1 = a0 + a2;   a2 = a0 + a1; (a) Let us study the instruction encoding for this question. Assume that 3 bits will be used for the opcode, and minimal space will be used to represent 128 bytes of addressable memory. Moreover, for the Register-Register ISA, there are only 5 general-purpose registers available.  Assume also a fixed-length instruction format, and that the memory is byte-addressable.

 For each of the four architectures, what is the number of bits required for the longest instruction? Hence, what is the size, in number of bytes, of the instructions?

             Partial answers are given below. Discuss.

 
Number of bits for longest instruction 
Number of bytes 
Stack 
10
2
Accumulator 
10
2
Memory-Memory 
 
4
Register-Register 
 
 
 

(b) What is the size (in number of bytes) of the code in question 2 for each of the four architectures? Which architecture is most efficient in terms of code size for this code?

 

4.      [Past-year’s exam question]

An ISA has 16-bit instructions and 5-bit addresses. There are two classes of instructions: class A instructions have one address, while class B instructions have two addresses. Both classes exist and the encoding space for opcode is completely utilized.  

(a)         What is the minimum total number of instructions?

(b)         What is the maximum total number of instructions?