CS207-Assignment 4 Solved

PART 1: DIGITAL DESIGN THEORY  

Provide answers to the following questions:  

1.     Write down the characteristic tables of both JK flip-flop and T flip-flop. Based on the truth table, write down their characteristic equations. (Use character T, J, K, Q, 

Qt+1) 

2.     A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z. The input and output equations are: 

𝐽𝐴 = 𝐵𝑥 + 𝐵′𝑦′      𝐾𝐴 = 𝐵′𝑥𝑦′       𝐽𝐵 = 𝐴′𝑥                       𝐾𝐵 = 𝐴 + 𝑥𝑦′  𝑧 = 𝐴𝑥′𝑦′ + 𝐵𝑥′𝑦′ 

(a)  Draw the circuit diagram. 

(b)  Write down the state table. 

(c)   Derive the state equations for A and B. 

3.     Use a D flip-flop, a 2x1 multiplexer, and a NOT gate to build a JK flip-flop. Draw the circuit diagram. Explain your design.  

4.     Derive the state table and the state diagram of the sequential circuit shown in the figure below. Explain the function that the circuit performs. 

  

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PART 2: DIGITAL DESIGN LAB 

INTRODUCTION
 

In this lab, you are required to use Vivado 2017.4 and Minisys/EGO1 Practice platform (xilinx FPGA chip artix 7 inside) to design a combinational Sequential circuit and test it. 

PREAMBLE
 

Before working on the course-work itself, you should master the following material.  

1.’ CH5-Synchronous Sequential Logic-SUSTC.ppt’ in Sakai site.  

2.     ‘Digital design lab10.pdf’, ‘Digital design lab11.pdf’ in Sakai site.   

3.     Verilog: http://www.verilog.com 

EXERCISE SPECIFICATION
 

TASK1:  

Implement a T Flip Flop with gates. Write a circuit to realize this function and test.  

•        Do the design (using structure design is suggested).  

•        Write testbench to verify the function of your design.  

•        Create the constraint file.  

•        Do the synthetic and implementation, generate the bitstream file and program the device, then test on the Minisys / EGO1 develop board.  

 

TASK2:  

Implement a circuit with 3 inputs (x_in(5bit-width), clk and an asynchronous reset) and 1 output (y_out (its bit-width is determined by the circuit designer)). If the asynchronous reset is valid, then state of y_out is A, otherwise the circuit get the value of x_in at every posedge of clk, If the total number of received 1 in x_in is a multiple of 2, then the state of y_out is B, otherwise the state of y_out is C.(the coding on A,B and C is determined by the circuit designer) 

•        Do the design by using FSM (DO NOT using 1-stage) in verilog. 

•        Write testbench to verify the function of your design. 

•        Create the constraint file 

•        Do the synthetic and implementation, generate the bitstream file and program the device, then test on Minisys /EGO1 the develop board