COL 216 Assignment 12: Simulating Cache Memory Solved

             

Computer Architecture (COL 216)
Assignment 12: Simulating Cache Memory

INDIVIDUAL (not group) ASSIGNMENT

[Substitute for Major examination]

You will be awarded marks according to your design and the test cases you developed to evaluate the design. Extensive testing is expected as a part of the Assignment

In this assignment you will develop a simulation software for cache memory. The simulated cache will have the functionality that was discussed in the cache memory lecture videos, but with a new Replacement Policy that works as follows. Each Cache Set is divided into two groups:

1.     One group contains the HIGH PRIORITY lines of the set

2.     The other group contains the LOW PRIORITY lines of the set

How is priority established? If a line is accessed again after the initial access that fetches it into the cache, it is promoted to the HIGH PRIORITY group. If a line is not accessed for sufficiently long (T cache accesses) after being moved to the HIGH PRIORITY group, it is moved to the LOW PRIORITY group. Within a priority group, the Least Recently Used policy may be used to manage the lines.

Make any reasonable assumptions you need. The above priority scheme is just an outline; it may not be complete. Feel free to add other details to make this work.

Inputs to the software will be: (inputs to be taken from input file)

1.     Cache size

2.     Cache line/block size 

3.     Cache associativity

4.     The value of T

5.     A sequence of memory access requests: Memory address, R or W (for Read or Write), and Data (if Write)

Outputs from the software will be: (output the content and cache statistics to output file)

1.     The complete content of the cache (Data, Tag, and Control bits of every cache line) in each Way after the memory access sequence is complete.

2.     Cache statistics: 

a.     Number of Accesses

b.     Number of Reads, Read Hits, and Read Misses

c.     Number of Writes, Write Hits, and Write Misses

d.     Hit Ratio

Deliverables:

1.     Software implementation of the cache described above

2.     Document describing the design. In the document, discuss your implementation of the replacement policy. Are the High and Low priority groups fixed in size? That is, in an 8way associative cache, are there 4 high-priority and 4 low-priority groups? Or some other break-up? Why? Can these sizes change at runtime?

Sample Input File:

Considered a very small cache size for demonstrating sample input and sample output. You are expected to consider different cache sizes and configurations.

 

Assumptions made :

1.  Out of 2 ways for each set, one way is assigned to high priority group and second way is assigned to low priority group.

2.  When valid status of the line is being modified to invald, the dirty status is left unmodified. 

When a line is being made invalid, modifying the dirty status is upto the implementation choice.