Taylan Unal (tuu2) and Joseph Brauckmann (jdb6064)
Project Overview:
The project of implementing a Virtual Memory Management Simulation proved to be a very difficult but interesting task. The idea was to implement the typical virtual memory hierarchy and simulate how an MMU would handle a series of instructions delivered to it.
To do this we created a variety of data structures that acted as a TLB, a DRAM, and a Page Table. Each demonstrating the events and states created from things like hits, misses, and even overall page faults. All of this information being displayed in the below statistics. But we also had to implement the correct outcomes of each event, including maintaining timings and creating an LRU algorithm for TLB entry replacement and page-replacement.
Experiment Type 1
Input total
number of context switche s total
number
of disk interrup ts total
number of TLB misses % of TLB
misses total
number of page faults % of page
faults total fraction of time in blocked state total
amount of time spent in
OS mode total
amount of time spent in user
mode
5 10 35 128 100% 35 25% 33% 184467
440736
395526
16 0
6 - - - - - - - - -
7 - - - - - - - - -
8 - - - - - - - - -
9 21 82 304 100% 82 30% 37% 187983
489932
988498
43 7
Experiment Type 2
Project Final Report
