CA2-Homework 3 Solved

Programming 

, we will use verilog to implement simple ALU, FPU and CPU in this 

We use Icarus Verilog to run the simulation, and we use gtkwave to check waveform. We will score your implementations under these settings.

Folder structure
                |-- ALU                                                                                 // Part 1

              |             |-- alu.f                                                                         <-- specify the files you use

              |            ‘-- codes                                                                       <-- put all the *.v here

              |          |                ‘-- alu.v

              |             |-- test_alu                                                              <-- run the test

              |              |-- testbench.v                                                         <-- test for corretness

              |              ‘-- testcases/                                                          <-- testcases

              |                            ‘-- generate.cpp                                          <-- used to generate testcases

                |-- FPU                                                                                 // Part 2

              |             |-- fpu.f

              |            ‘-- codes

              |          |                ‘-- fpu.v

              |             |-- test_fpu

              |              |-- testbench.v

              |              ‘-- testcases/

              |                            ‘-- generate.cpp

                ‘-- CPU                                                                               // Part 3

|-- cpu.f

‘-- codes

                          |                 |-- instruction_memory.v                        <-- instruction memory with access latency

                          |              |-- data_memory.v                                    <-- data memory with access latency

                          |               ‘-- cpu.v

|-- test_cpu

|-- testbench.v

‘-- testcases/

|-- generate.s

‘-- generate.cpp

ALU
The ALU spec is as follows:

Signal
I/O
Width
Functionality
i clk
Input
1
Clock signal
i rst n
Input
1
Active low asynchronous reset
i data a
Input
32
Input data A may be signed or unsigned depending on the i inst signal
i data b
Input
32
Input data B may be signed or unsigned depending on the i inst signal
i inst
Input
4
Instruction signal representing functions to be performed
i valid
input
1
One clock signal when input data a and b are valid
o data
Output
32
Calculation result
o overflow
Output
1
Overflow signal
o valid
Output
1
Should be one cycle signal when your results are valid
The test environment is as follows:

You are asked to implement the following functions in ALU:
i inst
Function
Description

4’d3
Signed Max
max(i data a, i data b) (signed)
4’d4
Signed Min
min(i data a, i data b) (signed)
4’4’d9
Unsigned Min
min(i data a, i data b) (unsigned)
4’d10
And
i data a & i data b
4’d11
Or
i data a | i data b
4’d12
Xor
i data a        i data b
4’d13
BitFlip
~ i data a
4’d14
BitReverse
Bit reverse i data a
More details:

•    We will compare the output data and overflow signal with the provided answers

•    For signed 32-bit integer Add, Sub, Mul, Max, Min

–   Two-input signal functions

–   Overflow signal only needs to be considered when Add, Sub or Mul is performed. For Max and Min, set the output overflow signal to 0.

–   We will not compare the return data with the answer provided when overflow happens

•    For unsigned 32-bit integer Add, Sub, Mul, Max, Min

–   Same criteria as signed operations’

•    Xor, And, Or, BitFlip, and BitReverse

–   Set output overflow signal to 0 when the above functions are performed.

–   Xor, And and Or are two-input signal functions.

–   BitFilp and BitReverse are one-input signal functions, therefore, i data b can be ignored.

FPU()
The FPU spec is as follows:

Signal
I/O
Width
Functionality
i  clk
Input
1
Clock signal
i  rst n
Input
1
Active low asynchronous reset
i  data a
Input
32
Single precision floating point a
i  data b
Input
32
Single precision floating point b
i  inst
Input
1
Instruction signal representing functions to be performed
i  valid
input
1
One clock signal when input data a and b are valid
o data
Output
32
Calculation result
o valid
Output
1
Should be one cycle signal when your results are valid
The test environment is as follows:
You are asked to implement the following functions in ALU:

i  inst
Function
Description
1’d0
Add
i data a + i data b (single precision floating point)
1’d1
Mul
i data a * i data b (single precision floating point)
Floating point: