Assignment 2 - EECS 211 Solution

Basics of Memory Protection
Problem 1
Right now, the LC3 VM does not differentiate between user and kernel model. In this problem, you need to change the LC3 VM to add a Supervisory Mode to the processor.
• Add a memory mapped register at location 0xFE04. This register will be called MR SM.
• Whenever MRSM has a value of 1, then the CPU is in the supervisory (kernel mode). Whenever MRSM has a value of 0, then the CPU is in the user mode.
• If the software tries to write any value on this register (for example by loading a value to the memory location 0xFE04) while the CPU is in the user mode, then the VM should refuse to execute such instruction, dump the memory into a file, and move to the next assembly instruction.
• Whenever a Trap instruction is executed, the MR SM register will be set automatically to 1
by the CPU.
• Whenever the CPU is in the kernel mode, then it should allow the software to write a value of 0 in the MR SM.
Deliverable
Append the OS from Assignment 1 to set the MR SM to 0 just before it switches from one process to another.
Write the code of 5 simple (dummy) processes that will be located in 0x4000, 0x5000, 0x6000, 0x7000, and 0x8000, respectively. These processes should perform the following instructions:
1. Load a certain value in the register R1. For example, the first process should load the value of “1“ into the register R1, the second process should load the value of “2” into the register R1, and so on.
2. Store the value inside the register R1 inside the memory location 0xFE04.
3. Store the value inside the register R1 inside the memory location 0x0200 (which is inside the OS memory).
4. Halt.
1
You will upload one file called “os.asm” and all memory dump files called “memory dump p2 1”, “memory dump p2 2”, ... that corresponds to the memory dumps issued during the switches between these processes.
Problem 2
In this problem, you need to change the virtual LC3 processor to add a simple Memory Protection Unit (MPU). An MPU is a trimmed down version of the Memory Management Unit (MMU) which supports the memory protection functionality without providing address translations. The MPU allows the privileged instructions (i.e., those executed whenever MR SM has a value of 1) to define memory regions and assign memory access permission and memory attributes to each of them. In this problem, you need to do the following:
• Add a memory mapped register at location 0xFE06. This register will be called MR MPU.
• Whenever MR MPU has a value of 0, then the software running on the CPU can access any memory location.
• Whenever MR MPU has a value of 1, then the software running on the CPU can access only memory locations between 0x3000 - 0x3FFF.
• Whenever MR MPU has a value of 2, then the software running on the CPU can access only memory locations between 0x4000 - 0x4FFF.
• Whenever MR MPU has a value of 3, then the software running on the CPU can access only memory locations between 0x5000 - 0x5FFF.
• Whenever MR MPU has a value of 4, then the software running on the CPU can access only memory locations between 0x6000 - 0x6FFF.
• Whenever MR MPU has a value of 5, then the software running on the CPU can access only memory locations between 0x7000 - 0x7FFF.
• Whenever MR MPU has a value of 5, then the software running on the CPU can access only memory locations between 0x8000 - 0x8FFF.
Deliverable
Append the OS to set the MR MPU with the right value before it switches to the process. Run the same 5 processes from the previous problem using your updated OS.
You will upload one file called “os.asm” and all memory dump files called “memory dump p2 1”, “memory dump p2 2”, ... that corresponds to the memory dumps issued during the switches between these processes.
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