CS39001 Assign-3: Verilog Design of Combinational and Sequential Unsigned Solved

CS39001
COMPUTER SCIENCE AND ENGINEERING
Computer Organization Laboratory
Assignment-3: Verilog Design of Combinational and Sequential Unsigned Multipliers

INSTRUCTIONS: Make one submission per group in the form of a single zipped folder containing your Verilog source code files(s) and Verilog testbench(es). Name your submitted zipped folder as Assgn 3 Grp <Group no.zip and (e.g. Assgn 3 Grp 25.zip). Inside each submitted source and testbench files, there should be a clear header describing the assignment no., problem no., semester, group no., and names of group members. Liberally comment your code to improve its comprehensibility.

1.   [Combinational Unsigned Binary Multiplier (Array Multiplier)] Design (using Verilog), simulate (using a proper Verilog testbench) and synthesize for any target FPGA platform supported by your version of Vivado,a combinational circuit (“Array Multiplier”) to multiply two 6-bit unsigned integers. For the general architecture of an array multiplier, please refer to the diagram uploaded on Moodle. Note down the hardware footprint and critical path delay of your synthesized design. The interface of your design should be:

module unsigned array mult (input [5:0] a, input [5:0] b, output reg [11:0]

       product);.                                                                                                                                                                                              (4 marks)

2.   [Sequential Unsigned Binary Multiplier (left-shift version)] Consider the iterative multiplication

                                                             n−1                                   n−1

of two n-bit unsigned integers, X = Xxj2j and Y = Xyj2j, to form the 2n-bit product P = X · Y .

                                                             j=0                                    j=0

Multiplication proceeds by calculating the partial products (associated with corresponding left-shifts) as: Pi+1 = Pi+xi2iY for each bit xi of the multiplier, with P0 = 0 and Pn = P. Design (using Verilog), simulate (using a proper Verilog testbench), and synthesize for any target FPGA platform supported by your version of Vivado, an 6-bit sequential unsigned binary multiplier following the above scheme. The input-side operand registers used in the datpath of your multiplier should have “parallel load” capabilities such that the 6-bit operands can be loaded in each of them instantaneously. Note down the hardware footprint and critical path delay of your synthesized design. The interface of your design should be:

module unsigned seq mult LS (input clk, input rst, input load, input [5:0] a, input [5:0] b, output reg [11:0] product);, where the signal names suggest their functionality. (7 marks)

3.   [Sequential Unsigned Binary Multiplier (right-shift version)] Now, design, simulate, and synthesize for any target FPGA platform supported by your version of Vivado, the above multiplier using an alternative scheme that considers right-shifting of the partial products:

Pi = Pi + xjY and Pi+1 = 2−1Pi

The interface should be module unsigned seq mult RS (input clk, input rst, input load, input

[5:0] a, input [5:0] b, output reg [11:0] product);.

      Other details remain the same.                                                                                                                                                  (7 marks)

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4.   Finally, submit a small 1-page report (in .pdf format) comparing the maximum speed of operation and hardware footprint of the above three designs. This report should be inside the zipped folder you submit.  (2 marks)