ASIC-Lab 1 Solved

Lab Manual

The purpose of this first lab exercise is to help you become familiar with the Verilog synthesizer, Design Compiler® (by Synopsis), and the Verilog simulator, QuestaSim® (by Mentor Graphics), that you will be employing throughout the class. In this lab, you will perform the following tasks:

•   Create a text file containing the Verilog source code for a 16-bit Comparator that determines whether A is greater than, less than, or equal to B.

•   Compile the source code and correct any syntax errors.

•   Simulate the Verilog model via QuestaSim®.

•   Synthesize the Verilog model utilizing Synopsis ’ Design Compiler®, via GNU Make automation.

•   Solve basic digital logic design problems.

•   Create ASIC Design style schematic block diagrams for basic ASIC building blocks.

•   Create ASIC Design style state transition diagrams for simple finite-state-machines (FSMs).

1 Required Background Knowledge and Forward Expectations
Throughout this course, it is assumed that you have rudimentary programming skills that are taught in a Freshman or Sophomore level structured/logical coding class. Also, a detailed understanding of digital logic design, both sequential and combinational, is required in order to complete the laboratory exercises. It should be noted that while we will be teaching you some Verilog syntax because it is needed in order to describe the more complex designs implemented in this course, the syntax itself is not the primary learning objective of this course. Therefore there will be times where you are expected to familiarize yourself with the simpler syntax from provided references. The digital logic design requirement includes, but is not limited to, Karnaugh Maps (K-Maps), Truth Tables, and State Machine design (both Moore and Mealy machines). This course will also serve as an introduction to writing scripts that are utilized by CAE tools in order to automate the process of using the tool. This automation will be in the form of having the scripts issue all the commands to the CAE tool as opposed to you entering the commands via the menu options or repeated command line calls. Through this exposure, it is hoped that you will find scripts to be a very efficient and time-saving mechanism in which to interact with the variety of CAE tools that they must utilize in this course. During the course of this semester you will be conducting 12 laboratory experiments on the workstations in the ASIC Design Laboratory. The laboratory experiments will be available for you to download in PDF format from Blackboard. You should read through the lab before coming to class. This will help you have an idea of the goal of the lab and the steps that will be necessary for its completion.

2 Account Setup
To begin this laboratory, you must login to a workstation. In order to do this, enter your mg account and password in the login window which should appear if you move the mouse. If you are unable to log into the machines in the EE 61 ASIC Design Lab please let your TA know immediately.

Once you are logged into the machine, the first step that needs to be performed is to setup your account so that you may access the variety of tools that will be required for this class throughout the remainder of the semester. Bring up a terminal window by holding down the right mouse button (RMB) and select “Open Terminal”. This should bring up a new window containing a command prompt. The first thing you should do is change your password. In your terminal window, issue the following command:

passwd

2.1     Account Setup
After completing the password change, issue the following command (make sure you are in your home directory):

~ece337/setup337

This batch/script file will copy the necessary setup files required to make Synopsis work properly into your root directory. If you have trouble with this step please ask for assistance from your TA. Failure to setup Synopsis properly will prevent you from being able to do the last part of this lab. Throughout the semester, you will encounter these commands to setup or copy information for tools. These are provided so you can get started working on your lab assignments rather than spending time copying source code into a file and possibly introducing errors.

Now whenever you open a new terminal window all the proper environment variables will be set up correctly for you to use the necessary tools. It is expected that you keep a very neat and orderly directory structure for this course. An organized directory structure will prove very useful during your project. You should, unless instructed to do otherwise, create a directory for each lab exercise that is assigned throughout the semester. This will serve as a good way for you to remember where the code or design for that lab is located, so that you may refer to them once you begin working on your project. If instructed to create any directory throughout this class, make sure that you use the case that is specified. This is required as some scripts to help you setup your accounts for the labs will be dependent on certain path names. Therefore, always be sure to name directories in the same case that they are given.

Exit the current terminal window and open a new terminal window to set up the changes.

2.2     Git Setup
The setup script should have created an ‘ece337’ folder in your home directory. It has also initialized this folder as a git repository so that all course work within it can be version controlled. If you already familiar with Git and have a remote repository/host you would like to use for the main/origin repository, please clone your origin repository as the ~/ece337 folder in your account instead or add your host repository as a remote for the one initialized in the ~/ece337 folder. Keep in mind that these repositories must be private repositories due to the nature of the tool scripts and source code you will be writing for the lab exercises. Now that your local repository is initialized, you may proceed with starting the first lab.

2.3      Lab 1 Specific Setup
Issue the following command in your new terminal to create the directory for this lab:

mkdir –p ~/ece337/Lab1

If you are not already aware, the “mkdir” command creates new directories. Also, the “-p” argument tells it to make any higher level directories it needs to in order to create the one at the end of the path, instead of exiting with an error if one of the folders in the path doesn’t already exist. Now, please change to your “Lab1 ” directory that you just created using the following command:

cd ~/ece337/Lab1

The next command that you will be issuing to the UNIX prompt is another script file. This script however is one that you will be using throughout the remainder of the semester and it would be a good idea to write a reminder to yourself to always run this script whenever you setup a new directory in which you plan to create a design. This command creates several directories inside the present working directory. The directories will be generated after issuing the command. In your terminal window, issue the following command:

dirset

Now list the contents of your directory by typing:

ls

Notice that the following directories now appear in your current directory:

Analyzed This directory will be used as the ’work’ directory when you begin working with the Synopsis design tools of Design Analyzer and Design Compiler®. This directory will actually be used to store the intermediate form of your design as you go from your Verilog source code to the output of the synthesis operation performed by the Synopsis tools.

Mapped This directory is where the results of your synthesis on your Verilog source code will be placed. Essentially, this directory will contain Verilog files that describe your synthesized or mapped circuits. A synthesized or mapped circuit is the results of linking or mapping your Verilog source code to a given set of logic gates in a design library. This mapped form of the Verilog code is actually the form that you could use to help generate the Layout for a chip so that it could be manufactured.

Reports This directory will contain the various reports that you instruct the tool to generate. These reports are text files which can contain several different types of information. For instance, a report file can be generated to detail the amount of area the circuit is utilizing in its current form. It could also contain a listing of the worst timing paths in the circuit. These paths are the ones in the circuit that have the largest time interval between the input and output signals for combination circuits, or the largest time delay between sequential elements, flip-flops or latches, in a sequential, clocked design. A report file could also contain a detailed breakdown of a timing path, so that one could see the delay of each gate in the timing path. Finally, another example of what could be contained in a report file is the power that the design dissipates.

Schematic This directory is where you will store the schematics of the mapped designs generated by Design Compiler®

Scripts This directory is where you will store the scripts used to manipulate the tools into performing the desired optimizations on the designs you are working.

Source This directory is where you should place all of your Verilog source code for the current design you are working on. This will give you one place to look for your source code in the given directory. It will also help the tools in searching for source code. If the source code is not located all in one directory, the search path for some scripts will not be able to find the code.

Docs This directory is where you should place all documents created as part of the lab or design, such as answers to questions, data sheets, and project reports

This directory structure is being used because it will help you in keeping all the files for your lab assignments and your project in a neatly ordered structure that will make it easy for you to find files. As the Synopsis tools run, they generate a large number of intermediate files which have the same name as your module. These files are also retained after they are created in order to speed up the processing time if you would need to re-analyze that particular design again. Therefore, it is advantageous for you if you keep a directory where all these files are stored, and this directory is kept separate from where your Verilog source code files are stored. In your case, that analyzed directory is where all the intermediate files are stored and the source directory is where all your Verilog files are stored. This directory structure will be enforced throughout the semester as the tools have been setup in such a fashion, so that their correct operation will be dependent upon the existence of the directories stated above. Therefore, whenever you create a new directory for this class or your project, make sure to run dirset in it to ensure your directories are setup properly.

Now that you have setup the folder for Lab 1 , please run the following lab setup script:

setup1

This setup script will check that you have indeed properly setup the directory for the Lab and will retrieve copies of the needed files for the lab. It should also move you to be in the “Lab1 ” folder if you were not already.

2.4        Initial Lab 1 Git Commit
Now that your Lab 1 directory has been initialized you need to tell the Git repository to start tracking its files. To do issue the following series of commands:

git add ~/ece337/Lab1 git ci -m “Initial setup for Lab 1 ”

The first command adds the folder and all currently contained files to be tracked by Git. The second command commits their current versions with the tag/log message “Initial setup for Lab 1 ”, to clarify the reason for the commit/check in to the Git repository. As you create new files during the lab you will need use the ‘git add’ and ‘git ci’ commands to add them for track. Only add your source code files, script files, makefile, and modelsim.ini file (the makefile and modelsim.ini are brought in through the add and commit of your initial lab folder setup). Adding generated or temporary files generally will cause problems with checking in updates, as well as wasting potentially large amounts of space in your accounts. For a more exhaustive list of git commands you can use ‘git help’, online resources, and/or the Git quick reference posted on blackboard.

Once you have set up your repository and added the Lab1 directory properly, have a TA check off your work.

3 Conventions
The course will use the following conventions for files, data structures, directories, and assistance in the labs.

3.1     File Names
Design Modules: All source files must be named after the module they contain (i.e., a design module called ’counter’ has a source file named ’counter.sv’).

Design Testbench: All testbench files must be named after a module with ’tb_’ prepended to the start of the module name (i.e., a design module called ’counter’ will have a testbench module named ’tb_counter’, and a corresponding source file called ’tb_counter.sv’).

3.2      Data Structures

Any types defined by the course or you should end with ’_t’. i.e. ’word_t’.

3.3     Getting Help
There will be queue setup via either a designated whiteboard or www.queuplive.com for each of the following:

Evaluation sign off You have your work done and are in need of TA initials. This means you are ready to show the results, not that you have a question on how to show, or what to do to show the results.

Questions You have questions on what, how, or why to do something. Even quick questions go here.

4 Compiling Verilog Code
Start a new terminal window and change directories until you are in the ece337/Lab1 directory. Simply type vsim –i

This will launch the program called QuestaSim®. This is the program that you will be using to simulate and verify that the various designs and you will be creating throughout this semester are correct. Once the window has opened, you will see a prompt inside the window, you must now type:

vlib work

This will create a folder in your Lab1 folder, which is necessary for compiling designs in QuestaSim®. You only need to do this once per directory. You must now compile your Verilog code for the comparator. In order to do this, type the following command at the QuestaSim® command prompt:

vlog source/comparator.sv

The compiler will now run. When the compiler finishes you will see several errors, indicated by the lines in the QuestaSim® window that are colored red. The code that was provided for the comparator had several intentional errors placed into it. This was done to introduce you to debugging the syntactical errors that you will undoubtedly encounter during this course. At this point, there are two ways you can view the Verilog code in order to correct the errors. One way is a standard text editor, such as nano, emacs, or vi. However, QuestaSim® has a built-in text editor that is highly useful in debugging due to the fact that it color codes the reserved words in the Verilog language (note that some versions of emacs and vi support Verilog highlighting also). This color coding helps one locate some common typographical errors that are encountered by students when creating Verilog source files.

The editor window will appear in the upper right portion of your screen once you have opened a file. In order to bring up your source code for the comparator, proceed to the file menu in the window that just appeared and select: File → Open...

Navigate into your “source” directory in the ‘Open File’ dialog box and choose your source file, comparator.sv, and select OPEN. Your code will now appear in the text window. At this point scroll through the source code in order to familiarize yourself with the colors that this editor assigns to different options of the code. You should also see the line numbers along the left of the page. Using that as a reference, return to your QuestaSim® Window and see what errors you have, the line number of the error is indicated in parenthesis in the QuestaSim® window. Begin to fix the errors that are present in the code based upon the line number information that is present in the QuestaSim® window.