HW4 Use VHDL on a 32 bit PG adder 25 pts

HW4 Use VHDL on a 32 bit PG adder 25 pts Everyone: First:Get yourself set up to use a VHDL compiler/simulator. To use the Cadence VHDL on linux.gl.umbc.edu. Follow instructions exactly or you figure out a variation. Be on some computer with ssh, Putty, TeraTerm. Type commands: ssh your-user-name@linux.gl.umbc.edu #or use Putty or TeraTerm (type in your password when asked) cp /afs/umbc.edu/users/s/q/squire/pub/download/cs411.tar . tar -xvf cs411.tar cd vhdl cp Makefile.cadence Makefile # only first time tcsh # or csh the following vhdl_cshrc will not work in bash source vhdl_cshrc make more add32_test.out # you should see added results make clean # saves a lot of disk quota Doing all your editing and work in directory /vhdl CMPE Computer Engineering Majors: You must design your own adder. The interface is the same and the file name must be add32.vhdl. Your adder must be an order square root of N adder. See hints in the handouts. Stage 1 has one delay, stage 2 has two delays, etc. Have exactly 32 bits of sum and carry out. The same test, given below, works for your adder. Possible hints: replace entity and architecture pg4 with fadd, a full adder and replace entity and architecture add4pg with c_sas that uses two fadd and some gates. Code main adder circuit down in architecture add32. See end of Lecture 7 Start by renaming add32_test.vhdl to add32.vhdl. Change "1 ns" to "1 ps" in two places, keep the fadd Build your c_sas 'entity' and 'architecture' after "fadd" and before 'entity add32'. Replace the internal part of 'architecture circuits of add32' with order square root adder. cp /afs/umbc.edu/users/s/q/squire/pub/download/tadd32.vhdl . tadd32.vhdl cp /afs/umbc.edu/users/s/q/squire/pub/download/tadd32.run . tadd32.run cp /afs/umbc.edu/users/s/q/squire/pub/download/tadd32.chk . tadd32.chk CMSC and other non CMPE Non Computer Engineering Majors: Now you need more starter files to do HW4: cp /afs/umbc.edu/users/s/q/squire/pub/download/add32pg_start.vhdl . cp /afs/umbc.edu/users/s/q/squire/pub/download/tadd32.vhdl . cp /afs/umbc.edu/users/s/q/squire/pub/download/tadd32.run . cp /afs/umbc.edu/users/s/q/squire/pub/download/tadd32.chk . If you are using a browser, rather than 'cp' then: Get add32pg_start.vhdl Then cp add32pg_start.vhdl add32.vhdl Then complete HW4 in add32.vhdl . Fill in for ... When finished with HW4 "submit" a single file named add32.vhdl that is a PG 32 bit adder. You will use the add32.vhdl file in the project, don't trash it. It is not important what the signal names are inside add32.vhdl, but keep the same interface, the entity declaration. You need a 32 bit adder, so use eight instances of add4pg and two instances of pg4 in an add32 architecture. Connect the circuit per the handout. The two 16 bit adders are connected end to end to make a 32 bit adder. cin goes into the first pg4, the carry out from the second pg4 gets the signal name cout. Use unique signal names or unique subscripts. All connections with the same name are tied together and have the same value. All For testing your add32 component use the Makefile and tadd32.vhdl and tadd32.run Use these commands to set up VHDL, then compile and simulate: On linux.gl.umbc.edu (you may use ssh to get there from some other computer.) You must ssh to one of these machines because the Cadence software is licensed to some specific machines. Each time you log on to do VHDL, type the commands: cd vhdl tcsh # optional if csh or tcsh is your default source vhdl_cshrc Then do your VHDL homework or project. Then do your own thing with Makefile for HW4, then HW6, project You can most easily use this directory for HW4, HW6, and the five parts of the project. Everyone: (Modify Makefile as shown below.) Add at end of the all: add32_test.out add tadd32.out Now having all: add32_test.out tadd32.out Makefile to modify somewhere with preceding and trailing blank lines, add: tadd32.out: add32.vhdl tadd32.vhdl tadd32.run ncvhdl -v93 add32.vhdl ncvhdl -v93 tadd32.vhdl ncelab -v93 tadd32:circuits ncsim -batch -logfile tadd32.out -input tadd32.run tadd32 Note: be sure commands are preceded by a tab, not spaces Now you can type "make" to run your add32.vhdl simulation. Check the file tadd32.out to be sure your adder worked. The answers are in tadd32.chk You can check your output with the command diff -iw tadd32.out tadd32.chk There should be no difference other than the copyright line. Submit ONE file add32.vhdl that has everything in it. submit cs411 HW4 add32.vhdl Your circuits must run. Incorrect results lose points. Debugging: Find the lowest bit that is wrong in the first output that does not compare. Proofread the numbers and signal names. if 'cout' is a 'U' rather than '0' or '1', there is a break in the adder chain. Unfortunately, the hex output converts 'U' undefined and 'X' don't know to zero, so you do not see the error. Follow the links below to Project and Download for more information. See the writeups on VHDL and sample circuits. The building blocks may become part of your final project.